Abstract: A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.

Abstract: An interconnect structure including a contact via in an interlayer dielectric, a first conductive feature in a first dielectric layer, the first dielectric layer over the interlayer dielectric, a first liner in the first dielectric layer, the first liner comprising a first part in contact with a sidewall surface of the first conductive feature, and a second part in contact with a bottom surface of the first conductive feature. The interconnect structure includes a first cap layer in contact with a top surface of the first conductive feature, a second conductive feature in a second dielectric layer, the second dielectric layer over the first dielectric layer, a second liner in the second dielectric layer, wherein the first and second conductive features comprise a first conductive material, and the contact via, first liner, first cap layer, and second liner comprise a second conductive material chemically different than the first conductive material.

Abstract: An electronic device includes a substrate, a plurality of electronic components and a conductive material. The electronic components are arranged on the substrate, and the electronic components respectively include a lower electrode, a semiconductor layer and an upper electrode, and they are sequentially stacked on the substrate. The electronic components share the semiconductor layer, and the semiconductor layer forms a plurality of connecting channels through the semiconductor layer. The connecting channels are located between the upper electrode of the first electronic component in the electronic components and the lower electrode of the second electronic component in the electronic components. These connecting channels are processed by lasers of different powers. The conductive material is arranged in the connecting channel so that the upper electrode of the first electronic component is electrically connected to the lower electrode of the second electronic component.

Abstract: A ring for clasping a cylindrical object includes a first element, a second element and a switch mechanism. The second element is circumferentially butted with the first element, and one end of the first element is adjacent to one end of the second element. The end of the second element has a protrusion protruding outwardly. The switch mechanism includes an abutting member adjacent to the end of the first element and configured to be rotated to abut against or move away from the protrusion of the end of the second element. When the abutting member is rotated and abuts against the protrusion of the end of the second element, the second element is fixed; when the abutting member is rotated and moves away from the protrusion of the end of the second element, the second element is released.

Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Abstract: The present disclosure discloses an image conversion apparatus having timing reconstruction mechanism. A receiving circuit receives a first interface image signal having input display data and horizontal blanking signals. A horizontal synchronization reconstruction circuit generates horizontal synchronization signals according to timings of the horizontal blanking signals. A vertical synchronization reconstruction circuit selects a predetermined timing of a predetermined signal between a frame initial timing and a display initial timing of the input display data, determines a timing of one of the horizontal synchronization signals behind and closest to the predetermined timing and generates a vertical synchronization signal accordingly. An image reconstruction circuit generates output display data according to the input display data and the horizontal synchronization signals.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A multimedia system and a protocol converter are provided. The multimedia system includes a sink device, e.g., a television, various audiovisual devices connected to the sink device, and the protocol converter. The protocol converter is connected to the sink device, and processes the audio and video signals inputted from a specific audiovisual source and outputted to the sink device to be played. The audio signals can be processed and played by an audio playback device directly connected with the protocol converter. Furthermore, the protocol converter can process the audio signals being returned from the sink device of the multimedia system via an audio return channel or an enhanced audio return channel. Finally, the received audio signals are converted and outputted to one of various audio output interfaces supported by the protocol converter.

Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

Abstract: A chemical mechanical polishing (CMP) apparatus is provided, including a polishing pad and a polishing head. The polishing pad has a polishing surface. The polishing head is configured to hold a wafer in contact with the polishing surface during the polishing process. The polishing head includes a retaining ring, at least one fluid channel, and a vacuum pump. The retaining ring is arranged along the periphery of the polishing head and configured to retain the wafer. The at least one fluid channel is provided inside the polishing head, wherein the retaining ring includes a bottom surface facing the polishing surface and a plurality of holes in fluid communication with the bottom surface and the at least one fluid channel. The vacuum pump is fluidly coupled to the at least one fluid channel.

Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Abstract: A method for CMP includes following operations. A first metal layer and a second metal layer are formed in a dielectric structure. The second metal layer is formed over a portion of the first metal layer. A first composition is provided to remove a portion of the first metal layer. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed to expose the second metal layer. A CMP operation is performed to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure.

Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.

Abstract: A light-emitting unit includes a substrate, a light-emitting element, and a micro lens. The light-emitting element is disposed on the substrate. The micro lens surrounds the light-emitting element. The micro lens includes compound eye structures adjacent to each other. In a top view, each compound eye structure has a length and a width, and the light-emitting element has a length and a width. The length and width of each compound eye structure in the top view and the length and width of the light-emitting element in the top view substantially satisfy 1?(L1/W1)/(L2/W2)?1.5, in which W1 is the width of the light-emitting element in the top view, L1 is the length of the light-emitting element in the top view, W2 is the width of each compound eye structure in the top view, and L2 is the length of each compound eye structure in the top view.

Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.

Abstract: Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.

Abstract: A semiconductor device includes an active layer having first and second active regions, first and second source electrodes, first and second drain electrodes, first and second gate electrodes, a first source metal layer, first and second drain metal layers, and a source pad electrically connected to the first source metal layer. The second drain metal layer is electrically connected to the second drain electrode and the first source metal layer. A projection of the second drain metal layer on the active layer forms a drain metal layer region. An projection of the source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a source/drain (S/D) epitaxial layer formed adjacent to the gate structure, and a dielectric spacer layer formed on the S/D epitaxial layer. The semiconductor structure includes a contact plug barrier formed over the S/D epitaxial layer, and a contact plug surrounding by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.

Abstract: A translation method configured to translate a device to hosts includes: according to a first control signal generated by the device, determining a first host and a second host from the hosts; generating a pseudo signal; transmitting a first data signal generated by the device to the first host, and transmitting the pseudo signal to the second host, so as to make the first host and the second host remain in a handshake completion state with the device at the same time.

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.