Abstract: To reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: A capacitor structure comprises a substrate having a first side, a second side opposite to the first side and an upper surface corresponding to the first side; a plurality of first trenches formed on the first side of the substrate, disposed along a first direction and a second direction parallel to the upper surface, and penetrating the substrate along a third direction, the first direction, the second direction and the third direction orthogonal to each other; a plurality of second trenches formed on the second side of the substrate and penetrating the substrate along the third direction, the first trenches and the second trenches separated from each other in the first direction; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

Abstract: This disclosure relates to a polishing composition that includes an abrasive, at least two pH adjusters, a barrier film removal rate enhancer, a low-k removal rate inhibitor, and an azole-containing corrosion inhibitor. This disclosure also features a method of using the polishing composition to polish a substrate containing copper and silicon oxide.

Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: The disclosure provides an electronic device. The electronic device includes a computer system, a light emitting module, and a control unit. The computer system is adapted to execute a boot procedure, the boot procedure lasting for a first time period. A light emitting module includes a plurality of indicator lights, each indicator light providing an indication function. The control unit is electrically connected to the light emitting module. The control unit controls the indicator lights to generate a first light emitting effect within a second time period when the computer system enters the boot procedure. The second time period is shorter than the first time period.

Abstract: A method for adjusting the uniformity of a display is provided. The method includes the following steps. An angle sensor is disposed on a display. The display opposite to a measurement device is disposed on a rotation axis. The uniformity of a frame of the display at at least one use angle is measured by the measurement device, wherein the display is adjusted to a first use angle and is left still for a period of time, so that the uniformity of the display arranged at the first use angle has a first uniformity correction parameter; and a correspondence table relevant to the first use angle and the first uniformity correction parameter is stored to the display.

Abstract: In some examples, the disclosure describes a device that includes a stand enclosure that includes a first end to interact with a work surface and a second end to be coupled to a display device, a plurality of input ports coupled to the stand enclosure, and a connection interface coupled to the second end of the stand enclosure to allow communication between the display device and the plurality of inputs when the connection interface is coupled to the display device.

Abstract: An integrated circuit includes a plurality of metal lines extending along a first direction, the plurality of metal lines being separated, in a second direction perpendicular to the first direction, by integral multiples of a nominal minimum pitch. The integrated circuit further includes a plurality of standard cells, at least one of the plurality of standard cells having a cell height along the second direction being a non-integral multiple of the nominal minimum pitch.

Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: An electric connector includes an insulative body, multiple conductive terminals, a shielding sheet, and a shielding shell. The insulative body includes a base and a tongue. The conductive terminals include an upper row of terminals and a lower row of terminals, which are disposed on an upper side and a lower side of the tongue, respectively. The shielding sheet is embedded in the insulative body and located between the upper row of terminals and the lower row of terminals. Two sides of the shielding sheet are extended with an extending section respectively. A distal end of each extending section is folded back to form an engaging portion. The shielding shell is adapted to sheathes the insulative body. Two sides of the shielding shell are respectively provided with an engaging trough engaged with one of the engaging portions to make the shielding shell contact with the shielding sheet.

Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.

Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.

Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.

Abstract: Method and apparatus for optimizing a convolutional neural network (CNN). A respective measure of importance is calculated for each of a plurality of elements within a CNN. A first one of the measures of importance is calculated by back propagating a second one of the measures of importance through the CNN. One or more of the plurality of elements is pruned from the CNN, based on the calculated measures of importance.

Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.

Abstract: A tool for verifying a user interface (UI) design of a mobile application receives a screenshot of the application's UI operating at a target device and retrieves a reference UI design image that corresponds to the received screenshot. The tool generates a plurality of images based on discrepancies between the screenshot and the reference UI design image. The plurality of images include a set of differential images in which each pixel location has a value that is based on a difference between corresponding pixels at the same pixel location of the reference UI design image and of the screenshot. The plurality of imagers also include at least one blended image that is an overlay of the reference UI design image with the screenshot.

Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.