Patents by Inventor Chun-Fu Chen

Chun-Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180286082
    Abstract: A tool for verifying a user interface (UI) design of a mobile application receives a screenshot of the application's UI operating at a target device and retrieves a reference UI design image that corresponds to the received screenshot. The tool generates a plurality of images based on discrepancies between the screenshot and the reference UI design image. The plurality of images include a set of differential images in which each pixel location has a value that is based on a difference between corresponding pixels at the same pixel location of the reference UI design image and of the screenshot. The plurality of imagers also include at least one blended image that is an overlay of the reference UI design image with the screenshot.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 4, 2018
    Inventors: Chun-Fu Chen, Paolo Girolami, Joseph W. Ligman, Marco Pistoia
  • Publication number: 20180174330
    Abstract: A tool for verifying a user interface (UI) design of a mobile application is provided. The tool receives a screenshot of the application's UI operating at a target device and retrieves a reference UI design image that corresponds to the received screenshot. The tool generates a plurality of images based on discrepancies between the screenshot and the reference UI design image. The plurality of images include a set of differential images in which each pixel location has a value that is based on a difference between corresponding pixels at the same pixel location of the reference UI design image and of the screenshot. The plurality of imagers also include at least one blended image that is an overlay of the reference UI design image with the screenshot.
    Type: Application
    Filed: December 20, 2016
    Publication date: June 21, 2018
    Inventors: Chun-Fu Chen, Paolo Girolami, Joseph W. Ligman, Marco Pistoia
  • Publication number: 20180076190
    Abstract: A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns. Each of the ECO cells in the array further includes a first central metal pattern overlapping the first metal pattern. Each of the ECO cells in the array further includes a via electrically connecting the first central metal pattern to the first metal pattern. The plurality of active area patterns is arranged symmetrically about the first central metal pattern.
    Type: Application
    Filed: November 16, 2017
    Publication date: March 15, 2018
    Inventors: Li-Chun TIEN, Ya-Chi CHOU, Hui-Zhong ZHUANG, Chun-Fu CHEN, Ting-Wei CHIANG, Hsiang Jen TSENG
  • Publication number: 20180039710
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20180039673
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Publication number: 20180039709
    Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Chun-Fu Chen, Jason L. Crawford, Ching-Yung Lin, Jie Lu, Mark R. Nutter, Toyotaro Suzumura, Ilie G. Tanase, Danny L. Yeh
  • Patent number: 9831230
    Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chun Tien, Ya-Chi Chou, Hui-Zhong Zhuang, Chun-Fu Chen, Ting-Wei Chiang, Hsiang Jen Tseng
  • Publication number: 20170255739
    Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Patent number: 9659129
    Abstract: An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Publication number: 20170068767
    Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Publication number: 20160365253
    Abstract: A system for processing a semiconductor wafer includes a database configured to store data including relationships between device pattern characteristics, chemical mechanical polishing (CMP) conditions, and CMP performance, a data analyzer configured to predict performance of a CMP process to be performed on a wafer based on wafer design data and the relationships included in the database, and an output device configured to output the predicted performance of the CMP process.
    Type: Application
    Filed: November 24, 2015
    Publication date: December 15, 2016
    Inventors: Kuang-Wei CHEN, Chun-Fu CHEN, Tuung LUOH
  • Patent number: 9501600
    Abstract: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 9431287
    Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: August 30, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yi Sheng Cheng, Chun Fu Chen, Yung Tai Hung, Chin Ta Su
  • Publication number: 20160143552
    Abstract: An electrocardiography signal extraction method includes receiving an electrocardiography signal, detecting a peak of a waveform of the electrocardiography signal, separating the waveform into left and right waves, normalizing the left wave and a plurality of scales of Gaussian function, comparing the normalized left wave with a left part of the normalized scales of Gaussian function, acquiring a left part error function, indicating a left minimum comparative error, selecting a left scale of Gaussian function with the left minimum comparative error, obtaining a left duration of the waveform, normalizing the right wave, comparing the normalized right wave with a right part of the normalized scales of Gaussian function, acquiring a right part error function, indicating a right minimum comparative error, selecting a right scale of Gaussian function with the right minimum comparative error, obtaining a right duration of the waveform, and obtaining an extracted wave.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 26, 2016
    Inventors: Gwo-Giun Lee, Jhen-Yue Hu, Chun-Fu Chen, Jhu-Syuan Ho
  • Patent number: 9325128
    Abstract: An electrical connector includes an insulation main body and a plurality of conductive terminals. The insulation main body is formed with a tongue. The tongue is formed with a first surface and a second surface opposite to the first surface. Each of the conductive terminals is installed in the tongue. Each of the conductive terminals is formed with a first contact part, a second contact part and a solder part. The first contact part is exposed on the first surface, and the second contact part is exposed on the second surface. The solder part is vertically connected to the first contact part or the second contact part and protruded out of the tongue. Accordingly, the electrical connector complying with the USB Type-C specification, allowing conductive terminals having the same definitions to be integrated and being specially used for power delivery is provided.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: April 26, 2016
    Assignee: JESS-LINK PRODUCTS CO., LTD.
    Inventors: Chun-Fu Chen, Yun-Chang Yang, Cheng-Chung Lai
  • Publication number: 20160093994
    Abstract: An electrical connector includes an insulation main body and a plurality of conductive terminals. The insulation main body is formed with a tongue. The tongue is formed with a first surface and a second surface opposite to the first surface. Each of the conductive terminals is installed in the tongue. Each of the conductive terminals is formed with a first contact part, a second contact part and a solder part. The first contact part is exposed on the first surface, and the second contact part is exposed on the second surface. The solder part is vertically connected to the first contact part or the second contact part and protruded out of the tongue. Accordingly, the electrical connector complying with the USB Type-C specification, allowing conductive terminals having the same definitions to be integrated and being specially used for power delivery is provided.
    Type: Application
    Filed: February 26, 2015
    Publication date: March 31, 2016
    Inventors: CHUN-FU CHEN, YUN-CHANG YANG, CHENG-CHUNG LAI
  • Patent number: 9245887
    Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Hui-Zhong Zhuang, Shang-Chih Hsieh, Li-Chun Tien
  • Patent number: 9202696
    Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Hang Yang, Chun-Fu Chen, Pin-Dai Sue, Hui-Zhong Zhuang
  • Patent number: 9158877
    Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 13, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 9125580
    Abstract: An electrocardiography signal extraction method is performed on a processor of a computer system and includes receiving an electrocardiography signal, performing a time-frequency transformation on the received electrocardiography signal to generate a corresponding scalogram, selecting a predetermined R-pertinent scale, performing the time-frequency transformation at the selected predetermined R-pertinent scale to generate a R-pertinent summarized response, obtaining a R peak position, selecting a predetermined QRS-pertinent scale, performing the time-frequency transformation at the selected predetermined QRS-pertinent scale, obtaining a Q peak position and a S peak position of the electrocardiography signal by finding relative maximum negative responses before and behind the R peak position respectively, obtaining a QRSon position and a QRSoff position by finding relative minimum second derivatives of the responses before the Q peak position and behind the S peak position, respectively.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: September 8, 2015
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Gwo Giun Lee, Jhen-Yue Hu, Chun-Fu Chen, Jhu-Syuan Ho