Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A distance between the silicide layer and the dielectric fin increases toward the base portion.

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain electrodes; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside, wherein the two metal plugs and the isolation structure form sidewalls of a trench; and a dielectric liner on the sidewalls of the trench, wherein the dielectric liner partially or fully surrounds an air gap within the trench.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: A method for managing a memory buffer, a memory control circuit unit, and a memory storage apparatus are provided. The method includes the following steps. Multiple consecutive first commands are received from a host system. A command ratio of read command among the first commands is calculated. The memory storage apparatus is being configured in a first mode or a second mode according to the command ratio and a ratio threshold. A first buffer is configured in a buffer memory to temporarily store a logical-to-physical address mapping table in response to the memory storage device being configured in the first mode, in which the first buffer has a first capacity. A second buffer is configured in the buffer memory in response to the memory storage device being configured in the second mode, in which the second buffer has a second capacity, which is greater than the first capacity.

Abstract: A processor chip includes a logic circuit. The logic circuit is configured to be coupled to an electronic device. A configuration of the logic circuit corresponds to a plurality of candidate configurations. The configuration of the logic circuit is switched among the candidate configurations, and the electronic device associates with the processor chip to implement a function corresponding to the configuration of the logic circuit. When the configuration of the logic circuit is a first configuration and the electronic device executes a first driver program, the function is a first network-connection function. When the configuration of the logic circuit is a second configuration and the electronic device executes a second driver program, the function is a second network-connection function different from the first network-connection function.

Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.

Abstract: A universal serial bus (USB) device includes a first storage device, a controller, and a second storage device. The first storage device is configured to store input packets to be transmitted to a USB host. The controller is configured to receive the input packets of the first storage device, respectively compute hash values of the input packets, and respectively label first identifiers in the input packets according to the hash values to correspond to one of cores of a central processing unit at the USB host end. Among the input packets, the input packets with the same hash value are labeled with the same first identifier. The second storage device is configured to store the input packets that are labeled with the first identifier. The controller is further configured to allow the input packets stored in the second storage device to be transmitted to the USB host.

Abstract: A method of manufacturing a semiconductor wafer is disclosed. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, after testing the one or more geometric parameter values, conditionally exposing the semiconductor wafer to one or more dopant species to form one or more additional implant layers on the semiconductor wafer, after forming the one or more additional implant layers, conditionally forming one or more additional circuit layers on the semiconductor wafer to form a plurality of functional electronic circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer with a wafer acceptance test (WAT) operation.

Abstract: A docking station for power management includes an integrated circuit, a first signal input/output (I/O) port, a network interface controller, and a first controller. The first signal I/O port is connected to a host controller of a host. When the host enters a sleep mode or a standby mode, the network interface controller is disconnected, or there is no network packet transmission, the integrated circuit cuts off a signal connection between the integrated circuit and the first signal I/O port, so that the host controller enters a deepest sleep state. When the network interface controller receives a wake-on-LAN signal, the network interface controller informs the first controller through a function pin, and the first controller wakes up the host controller through the first signal I/O port. The network interface controller controls, in response to the wake-on-LAN signal, the integrated circuit to re-establish the signal connection.

Abstract: A data transceiver device and an operation method are provided. The data transceiver device receives input data and transmits output data. The data transceiver device includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal according to the set time. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data according to an output data threshold value and the time-out signal. The control circuit adjusts the set time and/or the output data threshold value based on an initial condition and the state of the buffer circuit.

Abstract: A universal serial bus (USB) device includes a first storage device, a controller, and a second storage device. The first storage device is configured to store input packets to be transmitted to a USB host. The controller is configured to receive the input packets of the first storage device, respectively compute hash values of the input packets, and respectively label first identifiers in the input packets according to the hash values to correspond to one of cores of a central processing unit at the USB host end. Among the input packets, the input packets with the same hash value are labeled with the same first identifier. The second storage device is configured to store the input packets that are labeled with the first identifier. The controller is further configured to allow the input packets stored in the second storage device to be transmitted to the USB host.

Abstract: A method of social key recovery for a first communication device supporting blockchain technology with asymmetric cryptographic algorithm is disclosed. The method comprises transmitting a device identity of the first communication to a second communication on the blockchain, performing a verification operation with the second communication device, receiving a message including a verification code of the first communication device and a public key of the second communication device, from the second communication device, wherein the first message is encrypted with a public key of the first communication device, decrypting the message with a private key of the first communication device, to obtain the public key of the second communication device, and transmitting seed phrases encrypted with the public key of the second communication device for restoring a crypto wallet on the blockchain, to the second communication device.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: The present invention provides a hardware setting device and hardware setting method thereof. The hardware setting device is configured to: boot an operating system; retrieve at least one hardware setting corresponding to a peripheral device from a pre-boot memory; and configure the peripheral device according to the at least one hardware setting.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.