Patents by Inventor Chun-Hsiung Hung

Chun-Hsiung Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory and memory managing method
    Patent number: 9558818
    Abstract: A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to a third state representing a second data different from the first data, the method also includes changing the state of the second memory cell back to the second state.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: January 31, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin Yi Ho, Ming-Hsiu Lee, Chun Hsiung Hung, Hsiang-Lan Lung, Tien-Yen Wang
  • Method and apparatus for determining status element total with sequentially coupled counting status circuits
    Patent number: 9548135
    Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: January 17, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yih-Shan Yang, Shou-Nan Hung, Chun-Hsiung Hung, Yao-Jen Kuo, Meng-Fan Chang
  • Dynamic data density ECC
    Patent number: 9542268
    Abstract: A method for operating a memory includes receiving an input data set, saving a first level error correcting code ECC for the data in the input data set, saving second level ECCs for a plurality of second level groups of the data in the data set, storing the data set in the memory, and testing the data set to determine whether to use the first level ECC or the second level ECCs. The method includes, if the first level ECC is used, storing a flag enabling use of the first level ECC, else if the second level ECCs are used, storing a flag enabling use of the second level ECCs. The method includes storing the second level ECCs in a replacement ECC memory, and storing a pointer indicating locations of the second level ECCs in the replacement ECC memory.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: January 10, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Power source for memory circuitry
    Patent number: 9536575
    Abstract: An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: January 3, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wu-Chin Peng, Chun-Yi Lee, Ken-Hui Chen, Kuen-Long Chang, Chun Hsiung Hung
  • Threshold voltage grouping of memory cells in same threshold voltage range
    Patent number: 9536601
    Abstract: A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 3, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • ECC method for flash memory
    Patent number: 9535785
    Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: January 3, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Nai-Ping Kuo, Shih-Chang Huang, Chin-Hung Chang, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • Retention logic for non-volatile memory
    Patent number: 9514834
    Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: December 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Kuen-Long Chang, Ken-Hui Chen, Yu-Chen Wang
  • Memory device and operating method thereof for reducing interference between memory cells
    Patent number: 9508455
    Abstract: An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: November 29, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Method and apparatus for reducing erase time of memory by using partial pre-programming
    Patent number: 9502121
    Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: November 22, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Yi Lee, Kuen-Long Chang, Chun-Hsiung Hung
  • Array structure having local decoders in an electronic device
    Patent number: 9496015
    Abstract: An array structure includes: a plurality of first signal lines and a plurality of sub-arrays. Each of the sub-array includes: a second signal line, a plurality of third signal lines, a plurality of fourth signal lines, a plurality of local decoders at each intersection of the first signal lines, the second signal line and the third signal lines; and a plurality of array cells at each intersection of the first signal lines, the third signal lines and the fourth signal lines. Respective control terminals of the local decoders are implemented by the first signal lines. In response to a selection status of the first signal lines and the second signal line, one of the local decoders selects one of the third signal lines.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: November 15, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ming-Hsiu Lee, Chun-Hsiung Hung, Tien-Yen Wang
  • Circuit for voltage detection and protection and operating method thereof
    Patent number: 9490624
    Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: November 8, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • Difference L2P method
    Patent number: 9471485
    Abstract: A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 18, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Han-Sung Chen
  • Local word line driver
    Patent number: 9449666
    Abstract: A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: September 20, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Circuit with output switch
    Patent number: 9450577
    Abstract: An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 20, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Su-Chueh Lo, Tzu-Ting Chiu
  • Stabilization of output timing delay
    Patent number: 9444462
    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: September 13, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • Memory operation latency control
    Patent number: 9437264
    Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Han-Sung Chen, Ming-Chao Lin
  • Apparatus of supplying power while maintaining its output power signal and method therefor
    Patent number: 9423814
    Abstract: A power supply apparatus and a method for supplying power are provided. The method includes: providing a first power supply for outputting a first power signal; providing a second power supply for outputting a second power signal; and selectively charging the second power supply by using the first power supply.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: August 23, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Ting Hu, Chun-Hsiung Hung, Wu-Chin Peng, Kuen-Long Chang, Ken-Hui Chen
  • Plural operation of memory device
    Patent number: 9412460
    Abstract: An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: August 9, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Tzung Shen Chen, Shuo Nan Hong, Yi Ching Liu, Chun-Hsiung Hung
  • Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
    Patent number: 9396770
    Abstract: The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part; the different parts can be in different, neighboring memory cells. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: July 19, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Sung Chen, Chung-Kuang Chen, Chun-Hsiung Hung
  • MEMORY DEVICE AND OPERATING METHOD THEREOF FOR REDUCING INTERFERENCE BETWEEN MEMORY CELLS
    Publication number: 20160203878
    Abstract: An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 14, 2016
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung