Patents by Inventor Chun-Hsiung Hung

Chun-Hsiung Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RETENTION LOGIC FOR NON-VOLATILE MEMORY
    Publication number: 20160027522
    Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 28, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: CHUN-HSIUNG HUNG, NAI-PING KUO, KUEN-LONG CHANG, KEN-HUI CHEN, YU-CHEN WANG
  • Method and apparatus for reducing erase disturb of memory by using recovery bias
    Patent number: 9245644
    Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: January 26, 2016
    Assignee: Macronix International Co., Ltd
    Inventors: Chun-Hsiung Hung, Bo-Chang Wu, Kuen-Long Chang, Ken-Hui Chen
  • MEMORY PAGE BUFFER
    Publication number: 20160005481
    Abstract: Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.
    Type: Application
    Filed: September 14, 2015
    Publication date: January 7, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: CHUN-HSIUNG HUNG, CHI LO
  • MEMORY INTEGRATED CIRCUIT WITH A PAGE REGISTER/STATUS MEMORY CAPABLE OF STORING ONLY A SUBSET OF ROW BLOCKS OF MAIN COLUMN BLOCKS
    Publication number: 20150380112
    Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.
    Type: Application
    Filed: September 9, 2015
    Publication date: December 31, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: SHOU-NAN HUNG, CHI LO, CHUN-HSIUNG HUNG
  • Charge pump utilizing external clock signal
    Patent number: 9225240
    Abstract: A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: December 29, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Chuan-Ying Yu
  • ECC METHOD FOR DOUBLE PATTERN FLASH MEMORY
    Publication number: 20150370634
    Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.
    Type: Application
    Filed: September 1, 2015
    Publication date: December 24, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Chang Huang, Ken-Hui Chen, Chun-Hsiung Hung
  • Charge pump system
    Patent number: 9214859
    Abstract: In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are communicated between a integrated circuit with the charge pump and an external circuit.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: December 15, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Yung Feng Lin, Chun-Jen Huang, Tzeng-Huei Shiau, Chun-Hsiung Hung, Caiyun Wu, Qifang Wang
  • Memory architecture of 3D array with diode in memory string
    Patent number: 9214471
    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: December 15, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
  • Thermally assisted flash memory with diode strapping
    Patent number: 9214236
    Abstract: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: December 15, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Chun Hsiung Hung
  • Method and system for operating memory
    Patent number: 9208842
    Abstract: A method and a system for operating a memory are provided. The memory includes a plurality of memory cells which are configured to store data. The method includes the following steps. A counting number recorded in a counter is counted by 1, if the memory is written. The memory is set as a frequently using device, if the counting number recoded in the counter reaches a predetermined value.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 8, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Ken-Hui Chen, Kuen-Long Chang, Yu-Chen Wang, Chin-Hung Chang, Chia-Feng Cheng, Min-Hsiung Meng
  • Method and apparatus for the erase suspend operation
    Patent number: 9183937
    Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: November 10, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Ken-Hui Chen, Chun-Hsiung Hung, Kuen-Long Chang
  • REFERENCE AND SENSING WITH BIT LINE STEPPING METHOD OF MEMORY
    Publication number: 20150302922
    Abstract: A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 22, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: TIEN-YEN WANG, CHUN-HSIUNG HUNG, CHIA-JUNG CHEN
  • Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks
    Patent number: 9165680
    Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 20, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shuo-Nan Hung, Chi Lo, Chun-Hsiung Hung
  • Bit line bias circuit with varying voltage drop
    Patent number: 9159434
    Abstract: A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: October 13, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Staggered write and verify for phase change memory
    Patent number: 9159412
    Abstract: A method for storing a data value in a memory cell is provided. The data value includes one of a first data value and a second data value respectively represented by a first and a second programmable resistance ranges. The method includes, within a write cycle, storing the first data value in the memory cell by applying a first verify operation having a first verify period and a first write operation having a first write period, or storing the second data value in the memory cell by applying a second verify operation having a second verify period longer than the first verify period and a second write operation having a second write period shorter than the first write period. The write cycle is shorter than a sum of the first write period and the second verify period.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: October 13, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Tien-Yen Wang
  • Program method, data recovery method, and flash memory using the same
    Patent number: 9152557
    Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: October 6, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Shuo-Nan Hung, Han-Sung Chen
  • Current sensing type sense amplifier and method thereof
    Patent number: 9147480
    Abstract: The configurations of sense amplifier and methods thereof are provided. The proposed sense amplifier includes a switch circuit having a main control switch, a sensing switch and a holding switch, wherein the three switches have a first bias, a second bias and a third bias respectively, and an auxiliary control switch electrically connected to the holding switch to control an operation of the holding switch.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: September 29, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Memory device and method for programming memory cell of memory device
    Patent number: 9147487
    Abstract: A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias voltage is applied to the drain terminal for programming the memory cell, wherein the bias voltage varies with the specific cycle number range.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: September 29, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Reference and sensing with bit line stepping method of memory
    Patent number: 9147449
    Abstract: A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: September 29, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tien-Yen Wang, Chun-Hsiung Hung, Chia-Jung Chen
  • Retention logic for non-volatile memory
    Patent number: 9147501
    Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: September 29, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Nai-Ping Kuo, Kuen-Long Chang, Ken-Hui Chen, Yu-Chen Wang