Patents by Inventor Chun-Hsiung Hung

Chun-Hsiung Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POWER DROP DETECTOR CIRCUIT AND OPERATING METHOD OF SAME
    Publication number: 20160204772
    Abstract: A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage.
    Type: Application
    Filed: September 22, 2015
    Publication date: July 14, 2016
    Inventors: Kuan-Ming LU, Chun-Hsiung HUNG, Chun-Yi LEE, Ken-Hui CHEN, Kuen-Long CHANG
  • CHARGE PUMP CIRCUIT AND METHOD OF CONTROLLING SAME
    Publication number: 20160204695
    Abstract: A charge pump circuit includes a plurality of branches coupled in parallel, each branch including a plurality of sub-blocks coupled in series, and each sub-block including a unit pump circuit. The charge pump circuit also includes a plurality of clock transfer circuits coupled to corresponding ones of the plurality of branches for providing clock signals to the corresponding branches. The sub-blocks of different branches are enabled and driven by the clock signals at different times.
    Type: Application
    Filed: June 12, 2015
    Publication date: July 14, 2016
    Inventors: Wu-Chin PENG, Hsing-Yu LIU, Chun-Yi LEE, Ken-Hui CHEN, Kuen-Long CHANG, Chun Hsiung HUNG
  • POWER SOURCE FOR MEMORY CIRCUITRY
    Publication number: 20160203846
    Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.
    Type: Application
    Filed: October 7, 2015
    Publication date: July 14, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: WU-CHIN PENG, CHUN-YI LEE, KEN-HUI CHEN, KUEN-LONG CHANG, CHUN HSIUNG HUNG
  • DECODE SWITCH AND METHOD FOR CONTROLLING DECODE SWITCH
    Publication number: 20160204697
    Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.
    Type: Application
    Filed: April 22, 2015
    Publication date: July 14, 2016
    Inventors: Yi-Fan Chang, Chun-Yi Lee, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • POWER SOURCE FOR MEMORY CIRCUITRY
    Publication number: 20160203845
    Abstract: An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.
    Type: Application
    Filed: October 7, 2015
    Publication date: July 14, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: WU-CHIN PENG, CHUN-YI LEE, KEN-HUI CHEN, KUEN-LONG CHANG, CHUN HSIUNG HUNG
  • MEMORY OPERATION LATENCY CONTROL
    Publication number: 20160180903
    Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.
    Type: Application
    Filed: February 26, 2016
    Publication date: June 23, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: CHUN-HSIUNG HUNG, HAN-SUNG CHEN, MING-CHAO LIN
  • MEMORY REPAIR REDUNDANCY
    Publication number: 20160170853
    Abstract: An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chi Lo, Shuo-Nan Hung, Chun-Hsiung Hung
  • Non-volatile memory device and method for shortened erase operation during testing
    Patent number: 9368220
    Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 14, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen
  • CLOCK INTEGRATED CIRCUIT
    Publication number: 20160164525
    Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: CHUNG-KUANG CHEN, CHUN-HSIUNG HUNG, Han-Sung Chen
  • PAGE BUFFER CIRCUIT AND OPERATING METHOD OF SAME
    Publication number: 20160148692
    Abstract: A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first page buffer, and input data of at least one neighboring page buffer. The first page buffer is also configured to apply a bias corresponding to the input data of the first page buffer, and the input data of the at least one neighboring page buffer to a bit line.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Chung-Kuang CHEN, Han-Sung CHEN, Chun-Hsiung HUNG
  • Program verify with multiple sensing
    Patent number: 9349469
    Abstract: A sense circuit is coupled to a bit line of a memory array. Control circuitry coupled to the sense circuit controls a program operation for a memory cell. After a program phase in which the memory cell in the memory array is programmed, in a program verify phase the control circuitry causes the sense circuit to sense data stored on the memory cell multiple times during the program verify phase. The multiple times include a first time sensing data from the memory cell and a second time sensing data from the memory cell.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: May 24, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • THRESHOLD VOLTAGE GROUPING OF MEMORY CELLS IN SAME THRESHOLD VOLTAGE RANGE
    Publication number: 20160125922
    Abstract: A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 5, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • PROGRAM VERIFY WITH MULTIPLE SENSING
    Publication number: 20160099069
    Abstract: A sense circuit is coupled to a bit line of a memory array. Control circuitry coupled to the sense circuit controls a program operation for a memory cell. After a program phase in which the memory cell in the memory array is programmed, in a program verify phase the control circuitry causes the sense circuit to sense data stored on the memory cell multiple times during the program verify phase. The multiple times include a first time sensing data from the memory cell and a second time sensing data from the memory cell.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 7, 2016
    Applicant: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Programming method, reading method and operating system for memory
    Patent number: 9286158
    Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: March 15, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chien-Hsin Liu, Su-Chueh Lo, Kuen-Long Chang, Ken-Hui Chen, Chun-Hsiung Hung
  • Method and apparatus for reduced read latency for consecutive read operations of memory of an integrated circuit
    Patent number: 9281021
    Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: March 8, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Han Sung Chen, Ming Chao Lin
  • CIRCUIT FOR VOLTAGE DETECTION AND PROTECTION AND OPERATING METHOD THEREOF
    Publication number: 20160064921
    Abstract: A circuit for voltage detection and protection comprises a first block, a first voltage detector, a second block and a second voltage detector. The first block receives a first voltage supply. The first voltage detector detects the first voltage supply and generates a first detecting signal when detecting the first voltage supply level is out of the first operating voltage range. The second block receives a second voltage supply. The second voltage detector detects the second voltage supply and generates a second detecting signal when detecting the second voltage supply level is out of the second operating voltage range. The first block performs a protection operation on the circuit when monitoring at least one of the first and second detecting signals.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • Clock integrated circuit
    Patent number: 9270272
    Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: February 23, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Chun-Hsiung Hung, Han-Sung Chen
  • STABILIZATION OF OUTPUT TIMING DELAY
    Publication number: 20160049925
    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Applicant: Macronix International Co., Ltd.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS
    Publication number: 20160049178
    Abstract: The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part; the different parts can be in different, neighboring memory cells. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
    Type: Application
    Filed: August 24, 2015
    Publication date: February 18, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: HAN-SUNG CHEN, CHUNG-KUANG CHEN, CHUN-HSIUNG HUNG
  • LOW LATENCY MEMORY ERASE SUSPEND OPERATION
    Publication number: 20160042796
    Abstract: A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array comprises a plurality of blocks of memory cells, each block comprising a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 11, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: WEN-MING HSU, NAI-PING KUO, CHUN-HSIUNG HUNG