Patents by Inventor Chun Hsu
Chun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136463Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Applicant: EPISTAR CORPORATIONInventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
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Publication number: 20240136386Abstract: A chip package structure and a method for producing the same are provided. The method at least includes: providing a substrate; forming a mirror ink on the substrate; placing a chip upside-down on the substrate; forming soldering wires coupled with the chip and the substrate; forming a support body on the substrate; providing a package cover adhered to a top surface of the support body; performing a solidifying process in which a solidifying light beam is emitted to the mirror ink and the mirror ink reflects the solidifying light beam to the support body to solidify the support body; performing a packaging process in which a package layer is formed to cover the chip, an outer periphery of the support body, and the package cover; and performing a cutting process in which the package layer and the substrate are cut to form the chip package structure.Type: ApplicationFiled: March 15, 2023Publication date: April 25, 2024Inventors: LI-CHUN HUNG, JUI-HUNG HSU, CHIEN-CHEN LEE
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Publication number: 20240136202Abstract: A chip package structure and a method for producing the same are provided. The method at least includes: providing a substrate; placing a chip upside-down on the substrate; forming bonding wires coupled with the chip and the substrate; forming a support body on the substrate; providing at least one reflecting member at a periphery of the support body; providing a package cover adhered to a top surface of the support body; performing a solidifying process in which a solidifying light beam is emitted to the reflecting member and the reflecting member reflects the solidifying light beam to the support body to solidify the support body; performing a packaging process in which a package layer is formed to cover the chip, an outer periphery of the support body, and the package cover; and performing a cutting process to form the chip package structure.Type: ApplicationFiled: December 1, 2023Publication date: April 25, 2024Inventors: LI-CHUN HUNG, JUI-HUNG HSU, CHIEN-CHEN LEE
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Publication number: 20240136760Abstract: A waterproof electrical connector includes a connector body and a waterproof cap. The connector body includes a mating island surrounded by a ring groove. The mating island defines a mating face and plural passageways. The passageways receive conductive terminals and penetrate through the mating face. A soft cushion is set inside the waterproof cap. The connector body includes a collar portion. The collar portion is higher than the mating face and forms an entrance cavity around the ring groove. When the cap covers the connector body, the soft cushion penetrates into the entrance cavity to press and seal the mating face.Type: ApplicationFiled: October 18, 2023Publication date: April 25, 2024Inventors: JIAN-KUANG ZHU, KUO-CHUN HSU, YIN-CHAO XU, JIA-QING LIU
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Publication number: 20240136117Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.Type: ApplicationFiled: October 1, 2023Publication date: April 25, 2024Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HANG-CHUN LU, YA-WEN YANG, YU-TING HSU, WEI-ZHI HUANG
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Patent number: 11967652Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.Type: GrantFiled: February 16, 2023Date of Patent: April 23, 2024Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
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Publication number: 20240130246Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
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Publication number: 20240128216Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.Type: ApplicationFiled: January 4, 2023Publication date: April 18, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Ching-Chun Wang, Hsiao-Hui Tseng, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240126673Abstract: Methods and systems for status determination are disclosed. A computing device may determine a status of the computing device or another computing device. One or more actions may be taken based on the status of the computing device or the another computing device.Type: ApplicationFiled: October 3, 2023Publication date: April 18, 2024Inventors: Chun Hsu, Michael Horwitz, Chris Orogvany, Alfred Stappenbeck
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Publication number: 20240122319Abstract: A protective case which is suitable for electronic devices of various sizes includes a bottom case and a positioning element. The bottom case is configured to accommodate an electronic device. The bottom case includes a plurality grooves, and each of the grooves includes a plurality of positioning holes. The positioning element is fixed to one of the positioning holes according to the size of the electronic device.Type: ApplicationFiled: September 5, 2023Publication date: April 18, 2024Applicant: InnoCare Optoelectronics CorporationInventor: Chao-Chun Hsu
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Publication number: 20240128987Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.Type: ApplicationFiled: November 28, 2022Publication date: April 18, 2024Applicant: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
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Patent number: 11962328Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.Type: GrantFiled: November 28, 2022Date of Patent: April 16, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
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Publication number: 20240121373Abstract: Disclosed are an image display method and a 3d display system. The method is adapted to the 3d display system including a 3d display device and includes the following steps. A first image and a second image are obtained by splitting an input image according to a 3d image format. Whether the input image is a 3D format image complying with the 3D image format is determined through a stereo matching processing performed on the first image and the second image. An image interweaving process is enabled to be performed on the input image to generate an interweaving image in response to determining that the input image is the 3D format image complying with the 3D image format, and the interweaving image is displayed via the 3D display device.Type: ApplicationFiled: May 10, 2023Publication date: April 11, 2024Applicant: Acer IncorporatedInventors: Kai-Hsiang Lin, Hung-Chun Chou, Wen-Cheng Hsu, Shih-Hao Lin, Chih-Haw Tan
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Publication number: 20240122078Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
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Publication number: 20240120325Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.Type: ApplicationFiled: May 31, 2023Publication date: April 11, 2024Applicant: POWERTECH TECHNOLOGY INC.Inventors: Pei-chun TSAI, Hung-hsin HSU, Shang-yu CHANG CHIEN, Chia-ling LEE
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Patent number: 11956541Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.Type: GrantFiled: January 26, 2023Date of Patent: April 9, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chen-Hsien Fan, Sung-Mao Tsai, Yueh-Lin Lee, Yu-Chiao Lo, Mao-Kuo Hsu, Ching-Chieh Huan, Yi-Chun Cheng
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Patent number: 11957061Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
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Publication number: 20240114359Abstract: Apparatus and methods are provided for AI-ML model storage and transfer in the wireless network. In one novel aspect, the AI-ML model is stored at the AI server and transferred through the user plane (UP). In one embodiment, UE downloads the AI-ML model from the AI server through the UP connection. In one embodiment, the AI-ML model is updated at the RAN node, and the UE downloads the AI-ML model through the AI server. In another embodiment, the AI-ML model is updated at the UE, and the UE uploads the AI-ML model to the AI server through the UP connection. In another embodiment, the UE uploads the AI-ML model to the RAN through the AI server. In one embodiment, the UE mobility triggers the AI-ML model transfer. In one novel aspect, the AI dataset is shared and transferred among different entities through the UP connection or a new AI plane.Type: ApplicationFiled: September 14, 2023Publication date: April 4, 2024Inventors: Ta-Yuan Liu, Hao Bi, CHIA-CHUN HSU
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Publication number: 20240114385Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. In certain configurations, the UE establishes a connection supporting an extended reality (XR) application service with a base station. The UE reports, to the base station under a trigger condition, a buffer status report (BSR) to indicate a buffer size for data to be transmitted to the base station. The BSR includes information related to a corresponding BSR table. The UE receives a configuration instruction from the base station. The UE configures resources on the UE.Type: ApplicationFiled: September 12, 2023Publication date: April 4, 2024Inventors: Ming-Yuan Cheng, Pradeep Jose, Chia-Chun Hsu
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Publication number: 20240114380Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. In certain configurations, the UE establishes a connection supporting an extended reality (XR) application service with a base station. The UE reports, to the base station, a delay status report (DSR) to indicate a buffer size for data to be transmitted to the base station. The DSR includes timing information. The UE receives a configuration instruction from the base station. The UE configures resources on the UE according to the configuration instruction to transmit the data to the base station.Type: ApplicationFiled: September 13, 2023Publication date: April 4, 2024Inventors: Ming-Yuan Cheng, Pradeep Jose, Chia-Chun Hsu, Sheng-Yi Ho