Patents by Inventor Chun Hsu

Chun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230384030
    Abstract: The present disclosure is directed to a wafer drying system and method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the system comprises a wafer drying station configured to dispense a drying gas over one or more wafers to dry the one or more wafers, a valve configured to divert the drying gas to a first portion and a second portion, and an exhaust line configured to exhaust the first portion of the drying gas. The system further comprises a detector configured to receive the second portion of the drying gas and to determine a real time property of the second portion of the drying gas, and a control unit configured to control a feedback operation of the wafer drying station based on the real time property of the second portion of the drying gas.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun Hsu, Sheng-Wei Wu, Shu-Yen Wang
  • Patent number: 11828976
    Abstract: The present disclosure provides a backlight module, including a substrate, a plurality of light-emitting elements, a protective layer and a plurality of first dots. These light-emitting elements are disposed on the substrate. The protective layer is disposed on the substrate and the light-emitting elements, the protective layer has an upper surface and a lower surface opposite to the upper surface, and the upper surface of the protective layer is flat. The first dots are disposed on the upper surface of the protective layer and cover the light-emitting elements. A vertical projection area of each of the first dots on the substrate is larger than a vertical projection area of each of the light-emitting elements on the substrate, so as to reduce the thickness of the backlight module and reduce the dots alignment process.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 28, 2023
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Ming-Chun Hsu
  • Patent number: 11832520
    Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Chiao-Chun Hsu, Chung-Yi Yu
  • Publication number: 20230378221
    Abstract: The present disclosure relates to an image sensor integrated chip (IC). The image sensor IC includes one or more interconnects arranged within an inter-level dielectric (ILD) structure on a first side of a substrate. An image sensing element is arranged within the substrate. Sidewalls of the substrate form one or more trenches extending from a second side of the substrate to within the substrate on opposing sides of the image sensing element. A dielectric structure is arranged on the sidewalls of the substrate that form the one or more trenches. A conductive core is arranged within the one or more trenches and is laterally separated from the substrate by the dielectric structure. The conductive core is electrically coupled to the one or more interconnects.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 23, 2023
    Inventors: Cheng-Ying Ho, Wen-De Wang, Kai-Chun Hsu, Sung-En Lin, Yuh-Ruey Huang, Jen-Cheng Liu
  • Publication number: 20230374689
    Abstract: A method for manufacturing a package includes generating an electric field between an anode and a cathode in an electroplating solution to electroplate a substrate electrically connected to the cathode; depositing metal on a central region of the substrate with a first deposition rate; depositing metal on an outer region of the substrate with a second deposition rate lower than the first deposition rate; and reducing the first deposition rate.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia Chun HSU, Chin-Feng WANG
  • Patent number: 11822453
    Abstract: Methods and systems for status determination are disclosed. A computing device may determine a status of the computing device or another computing device. The status may be based on operational data. One or more actions may be taken based on the status of the computing device or the another computing device. For example, at least one computing task may be performed based on the status.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 21, 2023
    Assignee: Comcast Cable Communications Management, LLC
    Inventors: Chun Hsu, Michael Horwitz, Chris Orogvany, Alfred Stappenbeck
  • Patent number: 11814731
    Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
  • Publication number: 20230353971
    Abstract: Methods and systems for communication management are disclosed. A computing device may receive a computing request. The computing device may determine a timeout parameter associated with the computing request. A notification may be sent if the timeout parameter is predicted to be exceeded or if the timeout parameter is exceeded.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 2, 2023
    Inventors: Chun Hsu, Michael Horwitz, Chris Orogvany, Alfred Stappenbeck
  • Publication number: 20230346304
    Abstract: The present invention provides a method for OSA (Obstructive Sleep Apnea) severity detection using recording-based electrocardiography (ECG) Signal. The major feature of the present invention emphasizes on using a recording-based ECG Signal as an input, which is different from the deep learning-based prior art of using segment-based signals as an input to a model, and the segment-based signals has only two classification results, i.e. normal or apnea. The present invention provides a method for a model to detect and output directly a value of apnea-hypopnea index (AHI) for the OSA Severity.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Sin Horng Chen, Cheng Yu Yeh, Chun Cheng Lin, Shaw Hwa Hwang, Yuan Fu Liao, Yih Ru Wang, Kuan Chun Hsu, You Shuo Chen, Yao Hsing Chung, Yen Chun Huang, Chi Jung Huang, Li Te Shen, Bing Chih Yao, Ning Yun Ku
  • Publication number: 20230341111
    Abstract: A light box structure includes a bracket and a board. The bracket is in an arc shape and has a first surface and a second surface opposite to each other. The board has a plurality of magnetic positioning posts. The magnetic positioning posts have at least two different heights. The board is attracted and attached on the first surface of the bracket through the magnetic positioning posts.
    Type: Application
    Filed: December 30, 2022
    Publication date: October 26, 2023
    Inventors: Li-Yuan LIAO, Chien-Hsin LIN, Ming-Chun HSU, Yu-Chin WU
  • Publication number: 20230326951
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a semiconductor substrate. A dielectric structure is disposed on a first side of the semiconductor substrate. An isolation structure extends from the dielectric structure into the first side of the semiconductor substrate. The isolation structure laterally wraps around the photodetector and comprises an upper portion disposed above the first side of the semiconductor substrate and directly contacting sidewalls of the dielectric structure. The isolation structure comprises a first material different from a second material of the dielectric structure.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 12, 2023
    Inventors: Cheng-Ying Ho, Wen-De Wang, Keng-Yu Chou, Kai-Chun Hsu, Tzu-Hsuan Hsu, Jen-Cheng Liu
  • Patent number: 11784089
    Abstract: A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer includes a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsu Yen, Chen-Hui Yang, Yu Chuan Hsu
  • Publication number: 20230318695
    Abstract: Repeater and control method are provided for DL transmission and UL transmission between a BS and a UE. In one novel aspect, the repeater establishes a control link with the BS. Then, the repeater configures an amplify and forward link between the BS and the UE by at least one configuration of the control link.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 5, 2023
    Inventors: Cheng-Rung Tsai, Pei-Kai Liao, Chia-Chun Hsu, Francesc Boixadera-Espax, Per Johan Mikael Johansson, Tsang-Wei Yu
  • Publication number: 20230317459
    Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Chun-Hsu Yang, Huei-Wen Hsieh, Nai-Hao Yang, Yu-Cheng Hsiao, Chun-Sheng Chen, Che-Wei Tien, Kuan-Chia Chen
  • Publication number: 20230315922
    Abstract: Various examples described herein relate to a head mountable device (HMD) which comprises an input device to receive captured user data, a connection interface to exchange the user data with a host device, a privacy data switch to route the user data between the input device and the connection interface in the HMD, and a controller. The controller determines whether the user data is restricted data, directs the privacy data switch to block the exchange of the user data when it is determined that the user data is restricted data, and directs the switch to allow the exchange of the user data when it is determined that the user data is not restricted data.
    Type: Application
    Filed: September 21, 2020
    Publication date: October 5, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Kuan-Lin Li, Jen-Chun Hsu, Yew-Chung Hung
  • Publication number: 20230317758
    Abstract: An optical device with isolation structures and a method of fabricating the same are disclosed. The optical device includes a substrate having a first surface and a second surface opposite to the first surface, first and second radiation sensing devices disposed in the substrate, a first isolation structure disposed in the substrate. The first isolation structure has a first surface and a second surface opposite to the first surface. The optical device further includes a second isolation structure disposed in the substrate and on the first surface of the first isolation structure. The second isolation structure includes a metal structure and a dielectric layer surrounding the metal structure. The second isolation structure vertically extends over the first surface of the substrate.
    Type: Application
    Filed: August 2, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ying Ho, Kuan-Hua Lin, Keng-Yu Chou, Kai-Chun Hsu, Sung-En Lin, Wen-De Wang, Jen-Cheng Liu
  • Publication number: 20230307457
    Abstract: A semiconductor device having a standard cell comprises a first bottom transistor, a first top transistor, a second bottom transistor, a second top transistor, and a first bottom-transistor-level metal line. The first bottom transistor is in a first row. The first top transistor is disposed above the first bottom transistor in the first row. The first bottom transistor and the first top transistor share a first gate structure. The second bottom transistor is in a second row next to the first row. The second top transistor is disposed above the second bottom transistor in the second row. The second bottom transistor and the second top transistor share a second gate structure. The first bottom-transistor-level metal line extends laterally from a first source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.
    Type: Application
    Filed: July 22, 2022
    Publication date: September 28, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Wei-Cheng KANG, Tzu-Hsuan CHANG, Wei-Yang WENG, Yu-Tzu CHENG, Huang-Chun HSU, Yu-Jung LIAO
  • Publication number: 20230293592
    Abstract: Provided is a method for treating disorders or conditions related to erectile dysfunction. The method includes administering to a subject in need thereof a therapeutically effective amount of mesenchymal stem cells or secretome thereof, wherein the mesenchymal stem cells or secretome are derived from human amniotic fluid.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 21, 2023
    Inventors: Yi-No WU, Yu-Jen CHANG, Wen-Chun HSU, Shiaw-Min HWANG, Tzu-Hao HUANG
  • Publication number: 20230299541
    Abstract: A card edge connector includes: an insulating housing defining a card slot opening forwards through a front face thereof; plural terminals retained in the insulating housing and including contacting portions extending into the card slot and soldering portions exposed upon a bottom face of the housing; and a metal shell at least partially covering the insulating housing, wherein the metal shell including a flat plate and a pair of side plates bending downwards from the flat plate, and the flat plate is at least partially embedded in the insulating housing and located proximate to a top face.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 21, 2023
    Inventors: PO-FU CHEN, KUO-CHUN HSU, TA-LUNG LIU, MING-XIANG CHEN
  • Patent number: 11765988
    Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsu Yen, Yu-Chuan Hsu, Chen-Hui Yang