Patents by Inventor Chun-Hung Lin

Chun-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240250719
    Abstract: The present invention discloses an automatic signal deployer, a signal deployment system, an automatic signal path deployment method, and a behavior control signal generation method of a deployment agent. The signal deployment system includes an automatic signal deployer, a deployment agent and a base station. The deployment agent receives signal quality data, generates a behavior control signal according to the signal quality data, and sends out the behavior control signal to the automatic signal deployer. The automatic signal deployer receives the behavior control signal and a source signal coming from the base station, performs deployment according to the behavior control signal, whereby the automatic signal deployer can transmit the source signal toward a signal path allocation direction and complete automatic deployment of signal paths.
    Type: Application
    Filed: November 9, 2023
    Publication date: July 25, 2024
    Inventors: LI-HSIANG SHEN, KAI-TEN FENG, CHUN-CHIEH KUO, HUA-PEI CHIANG, CHYI-DAR JANG, TENG-CHIEH YANG, TSUNG-JEN WANG, CHI-HUNG LIN, CHI-EN CHIEN
  • Patent number: 12043770
    Abstract: A temporary bonding composition is provided. The temporary bonding composition includes a polyfunctional crosslinker, a polymer and a solvent. The polyfunctional crosslinker includes a compound containing at least two functional groups selected from the group consisting of blocked isocyanate groups, alkenyl ether groups, and alkoxyhydrocarbyl groups. Each of the blocked isocyanate groups is an isocyanate group blocked by a blocking agent. The polymer has a functional group reacting with the polyfunctional crosslinker.
    Type: Grant
    Filed: December 29, 2019
    Date of Patent: July 23, 2024
    Assignee: Daxin Materials Corporation
    Inventors: Cheng-Wei Lee, Pei-Ci Cho, Chun-Hung Huang, Min-Chi Yang, Chi-Yen Lin, Yuan-Li Liao
  • Patent number: 12043696
    Abstract: A zwitterionic resin is manufactured by a manufacturing method which includes the following steps. A first thermal process is performed on a first crosslinking agent and a choline having hydroxyl group or amino group to form a first mixture, in which the first crosslinking agent includes an isocyanate group. A second thermal process is performed on the first mixture, a second crosslinking agent, a chain extender, and an amino acid to form the zwitterionic resin, in which the chain extender includes a polyol.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: July 23, 2024
    Assignee: TAIWAN TEXTILE RESEARCH INSTITUTE
    Inventors: Chen-Shou Hsu, Sun-Wen Juan, Chun-Hung Lin
  • Patent number: 12046823
    Abstract: A communication device includes a nonconductive track, an antenna element, a first turning wheel, and a second turning wheel. The antenna element is disposed on the nonconductive track. The first turning wheel and the second turning wheel drive the nonconductive track according to a control signal, so as to adjust the position of the antenna element. The communication device provides an almost omnidirectional radiation pattern.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: July 23, 2024
    Assignee: HTC CORPORATION
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Patent number: 12046494
    Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: July 23, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wu-Hung Yen, Yi-Hsien Huang, Chun-Tang Lin, Shu-Hua Chen, Shou-Qi Chang
  • Publication number: 20240243097
    Abstract: A power module package structure includes a first substrate and a power component. The first substrate includes at least one conductive layer on a surface thereof. The power component includes a first chip and a first spacer. The first chip has at least one electrode. The first spacer in a heat dissipation space between the first substrate and the first chip includes an insulating heat dissipation layer in the heat dissipation space and multiple vertical conductive connectors, each of the vertical conductive connectors penetrates the insulating heat dissipation layer. The insulating heat dissipation layer surrounds the vertical conductive connectors and electrically isolates the vertical conductive connectors. The vertical conductive connector includes two opposite ends, one end electrically connected to the conductive layer, and the other end electrically connected to the electrode to form a conductive path and a heat dissipation path between the first chip and the first substrate.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 18, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, I-Hung Chiang, Chun-Kai Liu, Po-Kai Chiu, Hsin-Han Lin, Kuo-Shu Kao
  • Patent number: 12040354
    Abstract: A capacitor structure comprises a substrate having a first side, a second side opposite to the first side and an upper surface corresponding to the first side; a plurality of first trenches formed on the first side of the substrate, disposed along a first direction and a second direction parallel to the upper surface, and penetrating the substrate along a third direction, the first direction, the second direction and the third direction orthogonal to each other; a plurality of second trenches formed on the second side of the substrate and penetrating the substrate along the third direction, the first trenches and the second trenches separated from each other in the first direction; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chuan Hu, Chu-Fu Lin, Chun-Hung Chen
  • Patent number: 12041784
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Hon-Huei Liu, Chun-Hsien Lin
  • Publication number: 20240216833
    Abstract: A degassing tube includes a first plate, a second plate and a degassing tube. The first plate has a recess portion and a flange surrounding the recess portion. The flange has a first side and a second side opposite to the first side. A tube connector is disposed protrusively from the second side and located on the flange. The second plate covers the first plate. The degassing tube is disposed in the tube connector. The tube connector is formed with a degassing opening indented from the first side. The degassing opening has a maximum width defined in the tube connector and a minimum width defined on the first side. The minimum width is less than the maximum width for making the degassing tube tightly connected in the tube connector.
    Type: Application
    Filed: June 7, 2023
    Publication date: July 4, 2024
    Inventor: Chun-Hung LIN
  • Publication number: 20240200879
    Abstract: A separate capillary vapor chamber structure for dual heat sources is provided for transferring heat between low and high heat sources, and includes lower and upper plates covering each other, an evaporation area having the low and high heat sources, a first condensation area extended from a side of the evaporation area and adjacent to the low heat source, a second condensation area extended from another side of the evaporation area and adjacent to the high heat source. The lower plate has a lower capillary layer extended from the first condensation area to an end of the second condensation area through the evaporation area, and the upper plate has an upper capillary layer extended from an end of the first condensation area into the evaporation area to form a cut edge, such that the upper capillary layer is shorter than the lower capillary layer.
    Type: Application
    Filed: January 19, 2023
    Publication date: June 20, 2024
    Inventor: Chun-Hung LIN
  • Patent number: 11993674
    Abstract: A functional resin material is manufactured by the following reagents including a polyol, a polyamine, a first cross-linking agent, a second cross-linking agent, and a nanocellulose. Each of the first cross-linking agent and the second cross-linking agent includes an isocyanate block.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 28, 2024
    Assignee: TAIWAN TEXTILE RESEARCH INSTITUTE
    Inventors: Sun-Wen Juan, Chun-Hung Lin, Yi-Ching Sung
  • Publication number: 20240161843
    Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.
    Type: Application
    Filed: September 20, 2023
    Publication date: May 16, 2024
    Applicant: eMemory Technology Inc.
    Inventors: Chia-Fu Chang, Chun-Hung Lin, Jen-Yu Peng, You-Ruei Chuang
  • Publication number: 20240161323
    Abstract: The present disclosure provides a component matching and reporting method, which includes steps as follows. A 3D file is parsed to obtain features; the features is analyzed according to a feature analysis parameter to find out at least one component feature; it is judged whether the at least one component feature corresponds to a component according to a feature judgment parameter; when the at least one component feature corresponds to the component, the component is located; after the component is located, the component is measured to output a measurement report.
    Type: Application
    Filed: February 18, 2023
    Publication date: May 16, 2024
    Inventors: Ke-Min HU, Trista Pei-Chun CHEN, Chun-Hung LIN, Chun Chieh CHEN
  • Patent number: 11972800
    Abstract: A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second floating gate transistor and a second select transistor. The first select transistor is connected with a program source line and a program word line. The first floating gate transistor includes a floating gate. The first floating gate transistor is connected with the first select transistor and a program bit line. The second floating gate transistor includes a floating gate. The second floating gate transistor is connected with a read source line. The second select transistor is connected with the second floating gate transistor, the read word line and the read bit line. The floating gate of the second floating gate transistor is connected with the floating gate of the first floating gate transistor.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: April 30, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Chun Chen, Chun-Hung Lin
  • Publication number: 20240060724
    Abstract: The present disclosure discloses a vapor chamber and a supporting column securement structure thereof. The vapor chamber includes a housing and a supporting column securement structure. The housing includes a chamber. The supporting column securement structure includes a supporting mesh and a plurality of supporting columns. The supporting mesh is arranged inside the chamber and includes a plate with a plurality of mesh holes, and the plate includes a plurality of through holes formed thereon. The outer perimeter of the supporting column includes at least one positioning portion. Each supporting column penetrates through each through hole and is press-fitted at each one of the through holes via the positioning portion to be positioned on the supporting mesh. Accordingly, the supporting columns are precisely secured at the predefined locations, and the yield rate of the vapor chamber is increased.
    Type: Application
    Filed: June 7, 2023
    Publication date: February 22, 2024
    Inventor: Chun-Hung LIN
  • Patent number: 11892240
    Abstract: A combination structure of a vapor chamber and a heat pipe includes a half-shell seat element, a half-shell cover element, a wick structure, and a working fluid. The half-shell seat element includes a vapor chamber half-shell seat and multiple heat pipe half-shell seats. Each heat pipe half-shell seat is extended from the vapor chamber half-shell seat. The vapor chamber half-shell seat includes a vapor chamber cavity. Each heat pipe half-shell seat includes a heat pipe cavity. Each heat pipe cavity communicates with the vapor chamber cavity. The half-shell cover element is sealedly connected with the half-shell seat element. The wick structure is continuously laid on the vapor chamber half-shell seat and each heat pipe half-shell seat, and is formed in the vapor chamber cavity and each heat pipe cavity. The working fluid is disposed in the vapor chamber cavity.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN MICROLOOPS CORP.
    Inventor: Chun-Hung Lin
  • Publication number: 20240021246
    Abstract: A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.
    Type: Application
    Filed: May 9, 2023
    Publication date: January 18, 2024
    Applicant: eMemory Technology Inc.
    Inventors: Yu-Ping Huang, Chun-Hung Lin, Cheng-Da Huang
  • Publication number: 20230396615
    Abstract: A cross-tenant authentication system is described. The system receives a user token from a client device that is registered with a first tenant of a service application of a server. The system receives a request, from the client device, to access a second feature of a second tenant of the service application. The second feature of the second tenant of the service application is separate from a first feature of the first tenant of the service application. The second feature is only accessible to devices registered with the second tenant of the service application. The system authenticates the request by validating the user token from the client device and determines a cross-tenant policy of the second tenant of the service application based on the user token. The system forms an identity object based on the cross-tenant policy.
    Type: Application
    Filed: October 15, 2021
    Publication date: December 7, 2023
    Inventors: Chun Hung Lin, Vikas AHUJA, Matthias LEIBMANN, Anshul DUBE, Shankaranand ARUNACHALAM
  • Publication number: 20230371249
    Abstract: An antifuse-type one time programming memory cell at least includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure comprises a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.
    Type: Application
    Filed: March 13, 2023
    Publication date: November 16, 2023
    Inventors: Lun-Chun CHEN, Ping-Lung HO, Chun-Hung LIN
  • Patent number: D1026838
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN MICROLOOPS CORP.
    Inventor: Chun-Hung Lin