Patents by Inventor Chun-Hung Lin

Chun-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152515
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20210318552
    Abstract: An integrated image display device includes a display unit, a lens array layer, and a baffle assembly. The baffle assembly includes a first baffle layer and a second baffle layer. The first baffle layer includes a plurality of first baffles, and a first transmission portion is formed between each two adjacent ones of the first baffles. The second baffle layer includes a plurality of second baffles, and a second transmission portion is formed between each two adjacent ones of the second baffles. Portions of the first transmission portions overlapped with the second transmission portions form a plurality of light transmission units. An un-reconstructed image displayed by the display surface can be reconstructed by the lens array layer, and be recombined into an integrated image to form a stereo image.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 14, 2021
    Inventors: CHUN-HSIANG YANG, CHIH-HUNG TING, KAI-CHIEH CHANG, JUI-YI WU, HSIN-YOU HOU, TING-RU LIN
  • Patent number: 11145733
    Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: October 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Yu-Hsiang Lin, Po-Wen Su, Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
  • Publication number: 20210301426
    Abstract: A fiber masterbatch including a polyetherimide, a polyethylene terephthalate, and a polyimide is provided. A glass transition temperature of the polyimide is between 140° C. and 170° C., a 10% thermogravimetric loss temperature of the polyimide is between 500° C. and 550° C., and when the polyimide is dissolved in N-methyl-2-pyrrolidone and a solid content of the polyimide is 15 wt %, a viscosity of the polyimide is between 80 cP and 230 cP. A melt spun fiber obtained by using the fiber masterbatch is also provided.
    Type: Application
    Filed: September 29, 2020
    Publication date: September 30, 2021
    Applicant: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Shao-Yen Chang, Chun-Hung Lin, Yuan-Pei Liao, Yi-Cang Lai
  • Publication number: 20210307206
    Abstract: A vapor chamber structure includes a thin-sheet housing with a hollow interior and a capillary layer installed in the thin-sheet housing. The hollow interior of the thin-sheet housing is formed by an etching method, and plural first support portions are formed in the thin-sheet housing, and a first material layer and a second material layer are coated onto two inner walls of the thin-sheet housing respectively, and the capillary layer is attached onto the first material layer closely. With the first and second material layers coated onto the interior of the thin-sheet housing, the thin-sheet housing has a high structural rigidity.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventor: Chun-Hung LIN
  • Patent number: 11132031
    Abstract: An electronic device including a first body, a second body, a hinge structure, an electronic assembly and a linkage mechanism is provided. The first body and the second body are pivoted to each other through the hinge structure. The electronic assembly is disposed on the first body. The linkage mechanism is disposed in the first body and connected between the hinge structure and the electronic assembly. When the second body is closed to the first body, the electronic assembly is hidden between the first body and the second body. When the second body is opened relative to the first body with an opening angle less than a predetermined angle, the hinge structure does not drive the linkage mechanism. When the second body is opened relative to the first body with the opening angle not less than the predetermined angle, the hinge structure drives the linkage mechanism and the linkage mechanism drives the electronic assembly to be opened relative to the first body.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: September 28, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Che-Hsien Lin, Che-Hsien Chu, Ko-Yen Lu, Chun-Chieh Chen, Chen-Ming Lee, Yi-Hung Chen, I-Chien Huang
  • Patent number: 11133269
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Hao-Yi Tsai, Ming-Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Tzu-Sung Huang
  • Patent number: 11133418
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 28, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 11133187
    Abstract: A method for forming a photo-mask includes providing a first pattern, wherein the first pattern includes a first light-transmitting region and a first light-shielding region; transforming the first pattern into a second pattern, wherein the second pattern includes a second light-transmitting region and a second light-shielding region, the second light-transmitting region is located within range of the first light-transmitting region, and the second light-transmitting region has an area which is smaller than that of the first light-transmitting region, the second light-shielding region includes the entire region of the first light-shielding region, and the second light-shielding region has an area which is greater than that of the first light-shielding region; and forming the second pattern on a photo-mask substrate to form a photo-mask, wherein the photo-mask is used in an ion implantation process of a material layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 28, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chun-Hung Lin, Ching-Chun Huang, Chung-Chen Hsu
  • Publication number: 20210296183
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Publication number: 20210296182
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chi-Ting Wu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 11127837
    Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Patent number: 11125507
    Abstract: A heat dissipating apparatus using phase change heat transfer includes a box, a heat conductive block, a working fluid, and a heat transfer device. The box has a first shell plate and a second plate between both of which a chamber is defined. An opening is formed through the first shell plate. The heat conductive block is disposed corresponding to the opening; a portion of the heat conductive block is formed inside the chamber and the other portion of the heat conductive block is exposed out of the first shell plate. The working fluid is disposed in the chamber and in contact with the heat conductive block. The heat transfer device has an evaporator section installed inside the chamber to absorb the heat generated by the working fluid after phase change. Thus, the heat dissipating efficiency of the whole apparatus can be enhanced.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN MICROLOOPS CORP.
    Inventors: Chun-Hung Lin, Chun-Teng Chiu, Yi-Chung Chen, Chih-Wei Wang
  • Patent number: 11126247
    Abstract: A method for updating a power mode parameter combination, includes identifying a current hardware combination of a client host; loading and executing a current application program; loading a default profile according to the current application program to update a current power mode parameter combination of the current hardware combination; receiving a user-defined parameter combination to update the current power mode parameter combination of the current hardware combination; correlating the current application program, the current hardware combination and the updated current power mode parameter combination to generate a current profile as an updated default profile; and transmitting the current profile to a server as a candidate profile.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 21, 2021
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Ching-Hung Chao, Hou-Yuan Lin, Mou-Ming Ma, Chun-Kun Lan, Po-Chang Tseng, Hung-Yen Chen, Chun-Yu Wang, Yih-Neng Lin
  • Patent number: 11122077
    Abstract: Embodiments can provide a computer implemented method in a data processing system comprising a processor and a memory comprising instructions, which are executed by the processor to cause the processor to implement a system for network protection, the method comprising determining, by the processor, if an incoming connection comprising one or more packets has a false latency larger than a trigger latency; determining, by the processor, if an attack is currently in progress; and if the attack is in progress, injecting, by the processor, at least one of the one or more packets of the incoming connection or one or more packets of an outgoing connection with a false latency.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Hung Chou, Cheng-ta Lee, Yin Lee, Chun-Shuo Lin
  • Patent number: 11120997
    Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chiang Chen, Chun-Hung Lee, Ryan Chia-jen Chen, Hung-Wei Lin, Lung-Kai Mao
  • Patent number: 11121039
    Abstract: An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin, forming a first dummy gate over the first fin and a second dummy gate over the second fin, the first dummy gate and the second dummy gate having a same longitudinal axis, replacing the first dummy gate with a first replacement gate and the second dummy gate with a second replacement gate, forming a first recess between the first replacement gate and the second replacement gate, and a filling an insulating material in the first recess to form a second isolation region.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Jr-Jung Lin, Chun-Hung Lee
  • Publication number: 20210279159
    Abstract: A trace configuration calculating method is applied to pivotal connection of a first workpiece and a hinge. A first trace space is formed at a position where the hinge is pivoted to the first workpiece. A first trace is disposed through the first trace space. The trace configuration calculating method includes the hinge and the first workpiece rotating first and second angles to make the first trace space have first and second contour cross-sections respectively, overlapping the first and second contour cross-sections to form a first intersection area, calculating a first maximum inscribed circle according to the first intersection area, and determining a first optimal center and a first maximum diameter of the first trace according to the first maximum inscribed circle.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 9, 2021
    Inventors: Cheng-Hsin Chen, Chun-Hung Lin, Chun-Chieh Chen
  • Patent number: 11114060
    Abstract: A cursor image detection comparison and feedback status determination method is disclosed. The method is based on a non-invasive data-extraction system architecture, and uses an image processing unit to perform detection comparison on a cursor image shown on an operation screen outputted from a machine controller. The method includes steps of obtaining cursor foreground and background images set by a user, and selecting an algorithm to process the cursor foreground and background images to generate a cursor mask, and reading a cursor image and applying the cursor mask on the cursor image for pattern comparison, transmitting information of a comparison result and a cursor feedback status to a software control system, so as to provide a correction system to perform a cursor process program and check whether the movement of the cursor meet a position controlled by a feedback and correction system, thereby completing closed-loop control for the cursor.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 7, 2021
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Chao-Tung Yang, Wei-Hung Chen, Shih-Hsun Lin, Wei-Jyun Tu, Chun-Hong Liu, Chien-Chung Lin, Chieh-Yuan Lo, Hsiao-Ling Chang
  • Publication number: 20210268555
    Abstract: A plasma ashing method is provided. The plasma ashing method includes analyzing the process status of each of a number of semiconductor substrate models undergoing a tested plasma ash process by a residue gas analyzer. The tested plasma ash processes for the semiconductor substrate models utilize a plurality of tested recipes. The plasma ashing method further includes selecting one of the tested recipes as a process recipe for a plasma ash process.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 2, 2021
    Inventors: Chun-Jen HSIAO, Ya-Ping CHEN, Chien-Hung LIN, Wen-Pin LIU, Chin-Wen CHEN