Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

Abstract: This disclosure is related to an ultraviolet fluid sterilizing box structure. A box (10) includes a chamber (100), a water inlet (101) and a water outlet (102). The water inlet (101) and the water outlet (102) are located on different sides of the box (10). The partition (20) is disposed in the chamber (100) and includes an outer cylinder (21) and an inner cylinder (22). The outer cylinder (21) includes an outer cavity (210) and an inflow inlet (211). The inner cylinder (22) includes an inner cavity (220) and an opening (221). The ultraviolet module (30) is disposed on one side of the box (10) and includes a light-transmitting plate (31) and an ultraviolet lamp set (32). The light-transmitting plate (31) seals the outer cylinder (21). The ultraviolet rays irradiate the inner cavity (220) and the outer cavity (210).

Abstract: A light-emitting module (1) includes a light-emitting unit (10) and a rod lens (20). The light-emitting unit (10) outputs a light (11). The rod lens (20) is adjacent to the light-emitting unit (10), and converges the light (11) along an optical axis (100). A radial direction of the rod lens (20) is parallel to the optical axis (100). A distance between an axis (21) of the rod lens (20) and a light-emitting center (12) of the light-emitting unit (10) along the radial direction is greater than or equal to a focal length of the rod lens (20) along the radial direction.

Abstract: A circuit protection apparatus (100) is used to protect an LED drive circuit (200), and the circuit protection apparatus (100) includes a first switch unit (1) and a snubber circuit (3). The first switch unit (1) provides an electrical connection between an input terminal (100A) and the LED drive circuit (200) according to the normality of an input current (Iin) flowing through the input terminal (100A). The snubber circuit (3) provides a first delay time period (Td1) according to an input power (Vin). The snubber circuit (3) provides a start signal (Ss) to the LED drive circuit (200) according to the end of the first delay time period (Td1), and controls a first ground point (G1) of the snubber circuit (3) to be coupled to a second ground point (G2) of the LED drive circuit (200).

Abstract: This disclosure provides a rotary ultraviolet sterilizing box. A circuit board is disposed in the box. A rotary plate structure includes a motor and a carrier plate. The motor is disposed on a bottom of the box and electrically connected to the circuit board. The carrier plate is disposed in the box and driven by the motor to rotate. A linear LED light strip is arranged on an inner wall of the box and electrically connected to the circuit board. The linear LED light strip includes a plurality of ultraviolet LEDs arranged linearly and spacedly.

Abstract: The invention is a UV sterilizing box structure. A box body has a round chamber, an inlet, and an outlet. The round chamber is formed with an arc-shaped guiding channel. A UV light module is disposed on a side of the box body. An external fluid enters the round chamber via the inlet and spirally flows through an inside of the round chamber along the arc-shaped guiding channel so as to make the fluid in the box body generate a flow with a specific direction and stay for enough time to be sufficiently irradiated by UV rays. Thereby, a better effect of sterilization may be obtained.

Abstract: The invention is a UV sterilizing box structure. A box body has a round chamber, an inlet, and an outlet. The round chamber is formed with an arc-shaped guiding channel. A UV light module is disposed on a side of the box body. An external fluid enters the round chamber via the inlet and spirally flows through an inside of the round chamber along the arc-shaped guiding channel so as to make the fluid in the box body generate a flow with a specific direction and stay for enough time to be sufficiently irradiated by UV rays. Thereby, a better effect of sterilization may be obtained.

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

Abstract: An ultraviolet LED module and a container having the same are disclosed. The container includes a container cover, a container main body, and an ultraviolet LED module disposed on the container cover. The ultraviolet LED module includes: a case body, having a penetrated hole and not provided with a concave cup; an ultraviolet LED main body, having a LED die exposed in the penetrated hole; a waterproof and dustproof adhesive, filled in a gap between the ultraviolet LED main body and the case body for waterproofing and dustproofing; and an enclosing lens, enclosing the LED die; wherein ultraviolet generated by the LED die emits out from the penetrated hole through the enclosing lens. Accordingly, a power impairment of ultraviolet emitted by the LED die can be as lower as possible.

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

Abstract: A random bit cell includes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

Abstract: A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.

Abstract: A random bit cell incudes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

Abstract: A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.