Patents by Inventor Chun-Hung Lu
Chun-Hung Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8419217Abstract: The LED lamp includes a heat dissipating base, an LED module, a hood and a sealant. The heat dissipating base has a mount board including a first surface and a second surface. The first and second surfaces are provided with an annular trough and fins, respectively. The LED module is fixed on the mount board and surrounded by the annular trough. The hood is formed with a flange which is embedded into the annular trough to cloak the LED module. The sealant is filled in the annular trough to seal up.Type: GrantFiled: January 21, 2011Date of Patent: April 16, 2013Assignee: Hergy Lighting Technology Corp.Inventors: Chun-Hung Lu, Hong-Jyun Wang, Chia-Te Lin
-
Publication number: 20120299177Abstract: A semiconductor component structure is provided, which includes a body formed with openings, an insulating layer formed on surfaces of the body and the openings, conductive bumps formed in the openings, and a re-distributed circuit formed by conductive traces electrically connecting the conductive bumps, wherein the conductive traces are formed on a portion of the insulating layer on the body. As the conductive traces and the conductive bumps are formed on and in the body prior to the formation of the re-distributed circuit. The process for fabricating the semiconductor component structure is simplified and the reliability of the semiconductor component structure is enhanced. A method for fabricating the semiconductor component is also provided.Type: ApplicationFiled: September 23, 2011Publication date: November 29, 2012Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Chun Chieh Chao, Chun Hung Lu
-
Publication number: 20120224328Abstract: An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.Type: ApplicationFiled: May 20, 2011Publication date: September 6, 2012Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Huei-Nuan Huang, Pin-Cheng Huang, Chun-Hung Lu, Chun-Chieh Chao, Chi-Hsin Chiu
-
Publication number: 20120188766Abstract: The LED lamp includes a heat dissipating base, an LED module, a hood and a sealant. The heat dissipating base has a mount board including a first surface and a second surface. The first and second surfaces are provided with an annular trough and fins, respectively. The LED module is fixed on the mount board and surrounded by the annular trough. The hood is formed with a flange which is embedded into the annular trough to cloak the LED module. The sealant is filled in the annular trough to seal up.Type: ApplicationFiled: January 21, 2011Publication date: July 26, 2012Inventors: Chun-Hung Lu, Hong-Jyun Wang, Chia-Te Lin
-
Patent number: 8089798Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.Type: GrantFiled: November 30, 2009Date of Patent: January 3, 2012Assignee: eMemory Technology Inc.Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
-
Publication number: 20100073985Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.Type: ApplicationFiled: November 30, 2009Publication date: March 25, 2010Applicant: EMEMORY TECHNOLOGY INC.Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
-
Publication number: 20080296701Abstract: A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.Type: ApplicationFiled: December 14, 2007Publication date: December 4, 2008Applicant: eMemory Technology Inc.Inventors: Tsung-Mu Lai, Shao-Chang Huang, Wen-hao Ching, Chun-Hung Lu, Shih-Chen Wang, Ming-Chou Ho
-
Patent number: 7447082Abstract: A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.Type: GrantFiled: November 1, 2006Date of Patent: November 4, 2008Assignee: eMemory Technology Inc.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
-
Patent number: 7433243Abstract: A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.Type: GrantFiled: November 9, 2006Date of Patent: October 7, 2008Assignee: eMemory Technology Inc.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
-
Publication number: 20080138956Abstract: A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.Type: ApplicationFiled: December 21, 2007Publication date: June 12, 2008Applicant: EMEMORY TECHNOLOGY INC.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
-
Patent number: 7254086Abstract: The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.Type: GrantFiled: October 19, 2005Date of Patent: August 7, 2007Assignee: eMemory Technology Inc.Inventors: Ching-Yuan Lin, Hong-Yi Liao, Yen-Tai Lin, Shih-Yun Lin, Chun-Hung Lu
-
Publication number: 20070109861Abstract: A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.Type: ApplicationFiled: November 1, 2006Publication date: May 17, 2007Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
-
Publication number: 20070108507Abstract: A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.Type: ApplicationFiled: November 9, 2006Publication date: May 17, 2007Applicant: EMEMORY TECHNOLOGY INC.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
-
Publication number: 20070108470Abstract: A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.Type: ApplicationFiled: November 7, 2006Publication date: May 17, 2007Applicant: EMEMORY TECHNOLOGY INC.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
-
Publication number: 20070111357Abstract: A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.Type: ApplicationFiled: November 7, 2006Publication date: May 17, 2007Applicant: EMEMORY TECHNOLOGY INC.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
-
Publication number: 20070109869Abstract: A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.Type: ApplicationFiled: November 9, 2006Publication date: May 17, 2007Applicant: EMEMORY TECHNOLOGY INC.Inventors: Shih-Chen Wang, Hsin-Ming Chen, Chun-Hung Lu, Ming-Chou Ho, Shih-Jye Shen, Ching-Hsiang Hsu
-
Publication number: 20060262626Abstract: The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.Type: ApplicationFiled: October 19, 2005Publication date: November 23, 2006Inventors: Ching-Yuan Lin, Hong-Yi Liao, Yen-Tai Lin, Shih-Yun Lin, Chun-Hung Lu
-
Patent number: 7020036Abstract: A memory unit with sensing current stabilization includes: a memory cell; a reference cell for providing a reference current; a current mirror coupled to the memory cell and the reference cell for generating a differential current according to the reference current and a cell current of the memory cell; and a sense amplifier coupled to the current mirror for generating an output voltage according to the differential current.Type: GrantFiled: November 8, 2004Date of Patent: March 28, 2006Assignee: eMemory Technology Inc.Inventors: Chiun-Chi Shen, Chun-Hung Lu, Chien-Hung Ho
-
Publication number: 20060044902Abstract: A memory unit with sensing current stabilization includes: a memory cell; a reference cell for providing a reference current; a current mirror coupled to the memory cell and the reference cell for generating a differential current according to the reference current and a cell current of the memory cell; and a sense amplifier coupled to the current mirror for generating an output voltage according to the differential current.Type: ApplicationFiled: November 8, 2004Publication date: March 2, 2006Inventors: Chiun-Chi Shen, Chun-Hung Lu, Chien-Hung Ho
-
Patent number: 6307628Abstract: End point detection during a CMP process on a semiconductor wafer employs confocal optics to increase signal-to-noise ratio near the end point. The use of confocal optics for sensing reflected light from the wafer surface exhibits greater selectivity where intermediate layers of metal are present in the wafer. A laser diode is used as a light source to examine the wafer surface. Light reflected back to the laser diode reduces its power state, and this power state is sensed by a current detector which outputs a signal representative of reflected light intensity.Type: GrantFiled: August 18, 2000Date of Patent: October 23, 2001Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Chun-Hung Lu, Mei-Yen Li