Abstract: A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having opposite first and second sides and a plurality of conductive through holes communicating the first and second sides; forming an insulating layer on the first side of the substrate body, wherein the insulating layer has a plurality of openings correspondingly exposing the conductive through holes; and forming a plurality of conductive pads in the openings of the insulating layer, wherein the conductive pads are electrically connected to the corresponding conductive through holes, thereby dispensing with the conventional wet etching process and hence preventing an undercut structure from being formed under the conductive pads.

Abstract: A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having a chip mounting side and an opposite external connection side and a plurality of conductive through holes communicating the chip mounting side and the external connection side, wherein the chip mounting side of the substrate body is covered with a protection layer; performing a singulation process on the external connection side of the substrate body; bonding the substrate body to a carrier via the external connection side thereof; removing the protection layer; and removing the carrier to form a plurality of interposers, thereby simplifying the fabrication process and improving the product yield.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit.

Abstract: A controlling module controls illuminant state of an illuminant module according to a controlling signal sent form a wireless controller. The controlling module is electrically connected to the illuminant module and includes a microprocessor, a wireless receiver, a regulator, and a driving unit. The wireless receiver is electrically connected to the microprocessor and receives the controlling signal sent form the wireless controller. The regulator is electrically connected to the microprocessor. The driving unit is electrically connected to the microprocessor and the illuminant module.

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

Abstract: An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on a substrate in sequence, a modified extension doped region disposed in the substrate below the antifuse layer, and a first doped region and a second doped region disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate, a gate dielectric layer, a second doped region, and a third doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The second and the third doped region are respectively disposed in the substrate at two opposite sides of the select gate. The doped region, the antifuse layer and the antifuse gate form a varactor.

Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.

Abstract: A semiconductor substrate is provided, including: a substrate; a plurality of conductive through vias embedded in the substrate; a first dielectric layer formed on the substrate; a metal layer formed on the first dielectric layer; and a second dielectric layer formed on the metal layer. As such, when a packaging substrate is disposed on the second dielectric layer, the metal layer provides a reverse stress to balance thermal stresses caused by the first and second dielectric layers, thereby preventing warpage of the semiconductor substrate.

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

Abstract: A social data filtering system is provided. The social data filter system comprises a database, a retrieving module, a filtering module and a determining module. The database stores personal data and corresponding identification information. The retrieving module retrieves the personal data and the identification information corresponding to a designated person and generates search information accordingly to retrieve user information and corresponding social interaction information from a plurality of social data sources accordingly to the search information The filtering module performs filtering on the user information and the social interaction information according to the personal data to retrieve filtered information. The determining module determines at least one key word corresponding to the designated person according to the filtered information.

Abstract: A smart light emitting diode driving apparatus includes a micro processing unit and a light emitting diode driving circuit. An optical detection equipment is configured to send an optics characteristic signal to a computer after an optics characteristic of a light emitting diode is detected by the optical detection equipment. The computer is configured to send a control signal to the micro processing unit after the optics characteristic signal is processed by the computer. The micro processing unit is configured to record the control signal. The micro processing unit is configured to control the light emitting diode driving circuit in accordance with the control signal. The light emitting diode driving circuit is configured to output a driving current to drive the light emitting diode.

Abstract: An LED street structures includes a pair of frames, a plurality of LED modules, an electrical box, a side cover and a back cover. Each frame has a cover plate, a supporting plate and a blocking plate. The LED modules are arranged between the frames. Two sides of the LED modules are fixed on the supporting plate. The electrical box disposed by a lateral side of the LED modules covers one side of the frames. The side cover covers another side of the frames. The back cover positioned between the frames covers the LED modules.

Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.

Abstract: Disclosed is a bay lamp with a cooling plate. The bay lamp includes a metal lampholder and at least one cooling plate. Each cooling plate includes a vertical plate extended from the metal lampholder, a transverse plate bent and extended from the vertical plate, and a spacing formed between the transverse plate and the metal lampholder. The cooling plate is integrally formed with the metal lampholder and extended from the metal lampholder to substitute a conventional fin, so as to reduce the cost and weight of the bay lamp.

Abstract: A fabrication method of a package structure is provided, which includes the steps of: providing an interposer having a plurality of recess holes; forming a conductive bump in a lower portion of each of the recess holes; forming a conductive through hole on the conductive bump in each of the recess holes; removing a portion of the interposer so as for the conductive bumps to protrude from the interposer; and mounting at least a first external element on the conductive bumps, thereby simplifying the fabrication process, shortening the process time and reducing the material cost.

Abstract: A map system for presenting Point of Interest (POI) information is provided with an interface module, a storage unit, and a processing module. The interface module is coupled to a display device and provides an operation interface for receiving a search query and a condition of time period. The storage unit stores a plurality of POIs data and verified data of the POIs each corresponding to a respective one of different time periods. The processing module filters the POIs and the verified data according to the search query and the condition of time period to generate an electronic map, and displays the electronic map to present the filtered POIs via the interface module and the display device.

Abstract: A route recommendation system is provided. The system has: a data querying apparatus configured to generate query information according to a location; and a data analyzing apparatus, connected to the data querying apparatus, having: a database configured to store at least one candidate data, wherein each candidate data has a candidate location, at least one recommended location corresponding to the candidate location, and a recommended staying time of each recommended location; a data receiving unit configured to receive the query information; and a processing unit configured to generate at least one recommended route according to the query information and the candidate data, and transmit the at least one recommended route to the data querying apparatus, wherein the recommended route comprises a path from the location to the at least one recommended location, and the recommended staying time corresponding to each recommended location.

Abstract: An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.

Abstract: An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.