Patents by Inventor Chun-Hung Lu
Chun-Hung Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10459693Abstract: A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.Type: GrantFiled: July 27, 2018Date of Patent: October 29, 2019Assignee: EMEMORY TECHNOLOGY INC.Inventors: Chun-Hung Lin, Chun-Hung Lu, Shih-Chan Huang
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Publication number: 20190287928Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: ApplicationFiled: March 21, 2019Publication date: September 19, 2019Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Patent number: 10340228Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: GrantFiled: September 7, 2017Date of Patent: July 2, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Publication number: 20190114144Abstract: A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.Type: ApplicationFiled: July 27, 2018Publication date: April 18, 2019Inventors: Chun-Hung LIN, Chun-Hung Lu, Shih-Chan Huang
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Publication number: 20190109092Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit.Type: ApplicationFiled: December 11, 2018Publication date: April 11, 2019Inventors: Rui-Feng Tai, Hsiao-Chun Huang, Chun-Hung Lu, Hsi-Chang Hsu, Shih-Ching Chen
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Patent number: 10236227Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.Type: GrantFiled: December 24, 2015Date of Patent: March 19, 2019Assignee: Siliconware Prescision Industries Co., Ltd.Inventors: Lung-Shan Chuang, Ching-Wen Chiang, Tzung-Yen Wu, Chun-Hung Lu
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Publication number: 20190080778Abstract: A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.Type: ApplicationFiled: September 10, 2018Publication date: March 14, 2019Applicant: eMemory Technology Inc.Inventors: Kuan-Hsun Chen, Chun-Hung Lu, Ming-Shan Lo
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Publication number: 20180254232Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: ApplicationFiled: June 28, 2017Publication date: September 6, 2018Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
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Publication number: 20180135185Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: Po-Yi Wu, Chun-Hung Lu
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Publication number: 20180068959Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: ApplicationFiled: September 7, 2017Publication date: March 8, 2018Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Patent number: 9903024Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.Type: GrantFiled: April 16, 2015Date of Patent: February 27, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Po-Yi Wu, Chun-Hung Lu
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Patent number: 9786610Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: GrantFiled: August 12, 2015Date of Patent: October 10, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Publication number: 20170148761Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.Type: ApplicationFiled: January 6, 2017Publication date: May 25, 2017Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh
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Social data filtering system, method and non-transitory computer readable storage medium of the same
Patent number: 9607031Abstract: A social data filtering system is provided. The social data filter system comprises a database, a retrieving module, a filtering module and a determining module. The database stores personal data and corresponding identification information. The retrieving module retrieves the personal data and the identification information corresponding to a designated person and generates search information accordingly to retrieve user information and corresponding social interaction information from a plurality of social data sources accordingly to the search information The filtering module performs filtering on the user information and the social interaction information according to the personal data to retrieve filtered information. The determining module determines at least one key word corresponding to the designated person according to the filtered information.Type: GrantFiled: May 20, 2014Date of Patent: March 28, 2017Assignee: INSTITUTE FOR INFORMATION INDUSTRYInventors: Chun-Hung Lu, Yi-Hsung Li, Wen-Tai Hsieh, Tai-Hung Chen, Yu-Chi Chang -
Patent number: 9515048Abstract: A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having a chip mounting side and an opposite external connection side and a plurality of conductive through holes communicating the chip mounting side and the external connection side, wherein the chip mounting side of the substrate body is covered with a protection layer; performing a singulation process on the external connection side of the substrate body; bonding the substrate body to a carrier via the external connection side thereof; removing the protection layer; and removing the carrier to form a plurality of interposers, thereby simplifying the fabrication process and improving the product yield.Type: GrantFiled: June 19, 2015Date of Patent: December 6, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Kuang Wu, Tsung-Te Yuan, Chun-Hung Lu
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Publication number: 20160260644Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.Type: ApplicationFiled: December 24, 2015Publication date: September 8, 2016Inventors: Lung-Shan Chuang, Ching-Wen Chiang, Tzung-Yen Wu, Chun-Hung Lu
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Publication number: 20160147894Abstract: The present disclosure illustrates a method for filtering search results. The method comprises the steps of: receiving a keyword; searching by the keyword to obtain an initial search result which comprises a plurality of web pages, and searching at least one related word corresponding to the keyword; clustering the related word to generate a clustered result which comprises at least one clustered group; providing the clustered result to an user such that the user selects one clustered group from the clustered group; and filtering the initial search result based upon the selected clustered group to generate a filtered search result.Type: ApplicationFiled: December 10, 2014Publication date: May 26, 2016Inventors: CHUN-HUNG LU, JIN-GU PAN, YI-HSUN LI, TAI-HUNG CHEN
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Publication number: 20160141255Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: ApplicationFiled: August 12, 2015Publication date: May 19, 2016Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Patent number: 9324381Abstract: An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on a substrate in sequence, a modified extension doped region disposed in the substrate below the antifuse layer, and a first doped region and a second doped region disposed in the substrate at two opposite sides of the antifuse gate. The select transistor includes a select gate, a gate dielectric layer, a second doped region, and a third doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The second and the third doped region are respectively disposed in the substrate at two opposite sides of the select gate. The doped region, the antifuse layer and the antifuse gate form a varactor.Type: GrantFiled: January 27, 2015Date of Patent: April 26, 2016Assignee: eMemory Technology Inc.Inventors: Meng-Yi Wu, Hsin-Ming Chen, Chun-Hung Lu
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Patent number: 9305021Abstract: A map system for presenting Point of Interest (POI) information is provided with an interface module, a storage unit, and a processing module. The interface module is coupled to a display device and provides an operation interface for receiving a search query and a condition of time period. The storage unit stores a plurality of POIs data and verified data of the POIs each corresponding to a respective one of different time periods. The processing module filters the POIs and the verified data according to the search query and the condition of time period to generate an electronic map, and displays the electronic map to present the filtered POIs via the interface module and the display device.Type: GrantFiled: May 31, 2013Date of Patent: April 5, 2016Assignee: INSTITUTE FOR INFORMATION INDUSTRYInventors: Ren-Dar Yang, Chun-Hung Lu, Yi-Hsun Lee, Wen-Nan Wang, Tai Hung Chen