Abstract: A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states RH and RL, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by RH and RL, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.

Abstract: A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.

Abstract: A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.

Abstract: Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.

Abstract: A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.

Abstract: Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).

Abstract: The present disclosure provides a MTJ stack for an MRAM device. The MTJ stack includes a pinned ferromagnetic layer over a pinning layer; a tunneling barrier layer over the pinned ferromagnetic layer; a free ferromagnetic layer over the tunneling barrier layer; a conductive oxide layer over the free ferromagnetic layer; and a oxygen-based cap layer over the conductive oxide layer.

Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

Abstract: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

Abstract: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device and a word line selector having a source-drain path serially coupled to the MTJ device. A negative substrate bias voltage is connected to a body of the word line selector to increase the drive current of the word line selector. The threshold voltage of the word line selector is also reduced.

Abstract: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

Abstract: A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.

Abstract: A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.

Abstract: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.

Abstract: A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the value is rewritten into the MRAM cell.

Abstract: A multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.

Abstract: Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).

Abstract: A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 ? to 400 ?. The MTJ cell structure can have a top conducting layer over the sacrifice layer.

Abstract: The present disclosure provides a semiconductor memory device. The device includes a bottom electrode over a semiconductor substrate; an anti-ferromagnetic layer disposed over the bottom electrode; a pinned layer disposed over the anti-ferromagnetic layer; a barrier layer disposed over the pinned layer; a first ferromagnetic layer disposed over the barrier layer; a buffer layer disposed over the first ferromagnetic layer, the buffer layer including tantalum; a second ferromagnetic layer disposed over the buffer layer; and a top electrode disposed over the second ferromagnetic layer.

Abstract: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device and a word line selector having a source-drain path serially coupled to the MTJ device. A negative substrate bias voltage is connected to a body of the word line selector to increase the drive current of the word line selector. The threshold voltage of the word line selector is also reduced.