Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.

Abstract: A system module applied to the machine controller for simulating a machine operation screen based on a non-invasive data-extraction system, is disclosed. An image capture device of the system module can receive an original operation screen outputted from the machine controller, and transmit the original operation screen to the non-invasive data-extraction system and a high-speed image process unit for extraction of the information shown on the operation screen. The software control system can extract the operational information of the machine controller in real time, to create a machine operation flow for generating a simulated machine operation screen which is then outputted to a screen of the machine controller. As a result, the site working staff can be provided with operational information associated with the machine in real time, for example, the operational information includes currently executed operation screen, position of mouse cursor and pop-up window detection result.

Abstract: A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.

Abstract: This application provides an oral pharmaceutical composition in a solid form comprising amlodipine or a pharmaceutically acceptable salt thereof, a low dose range of dextromethorphan or a pharmaceutically acceptable salt thereof, and one or more pharmaceutically acceptable excipients. The composition is useful for treating hypertension.

Abstract: A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer.

Abstract: A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.

Abstract: A method for analyzing IR drop and EM of an IC is provided. A layout of an IC is obtained, wherein the layout is divided into a plurality of blocks, and each of the blocks corresponds to a specific function. Power-related information of the blocks is obtained. A specific operation power and a specific operation temperature are obtained according to the power-related information of each of the blocks. Each of the blocks is verified according to the corresponding specific operation power and the corresponding specific operation temperature.

Abstract: A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitridation process is performed on the gate dielectric layer. A multi-step post nitridation annealing process including two oxygen-containing annealing steps with different respective annealing temperatures is performed on the gate dielectric layer.

Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.

Abstract: A novel fixation method is presented that will circumvent both biological and safety concerns with current fixation methods.

Abstract: A frequency control circuit, adapted to be utilized in a phase locked loop circuit. The frequency control circuit includes a first frequency control block, a second frequency control block, a pump control unit and a charge pump unit. The first frequency control block generates a first control signal according to a frequency of an output signal from the phase locked loop circuit, in which the first control signal is configured to control the frequency of the output signal located within a predetermined frequency region. The second frequency control block generates a second control signal according to a frequency of an input signal and the frequency of the output signal, in which the second control signal is configured to control the frequency of the output signal located at a target frequency.

Abstract: The method of forming a semiconductor device is provided. A substrate having an exposed oxide layer is provided. A nitridation process is performed for the oxide layer. After the nitridation process, a plasma treatment containing an inert gas is performed for the oxide layer. A conductive layer is formed on the oxide layer.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad.

Abstract: Certain embodiments are directed to methods of measuring single cell levels of biomarkers associated with prostate cancer.

Abstract: A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.

Abstract: A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the semiconductor device, and directly under the metal pad.