Patents by Inventor Chun-Lien Su

Chun-Lien Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088054
    Abstract: A carrier structure is provided with a plurality of package substrates connected via connecting sections, and a functional element and a groove are formed on the connecting section, such that the groove is located between the package substrate and the functional element. Therefore, when a cladding layer covering a chip is formed on the package substrate, the groove can accommodate a glue material overflowing from the cladding layer to prevent the glue material from contaminating the functional element.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 14, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shu-Ting LAI, Chiu-Lien LI, Che-Min SU, Chun-Huan HUNG, Mu-Hung HSIEH, Cheng-Han YAO, Fajanilan Darcyjo Directo, Cheng-Liang HSU
  • Patent number: 11861012
    Abstract: A method provides the capability to maintain integrity of a data image stored by computing a hash value (“digest”) of the data image and comparing the hash value computed for the data image with a hash value computed for the data image and kept in a non-volatile area of memory. Bit flips in the data image that are a result of memory hardware errors reveal themselves as differences in the digest computed for the data image and the computed digest for the data.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: January 2, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chun-Lien Su
  • Patent number: 11734181
    Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: August 22, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan Hung, Chun-Lien Su
  • Publication number: 20230244500
    Abstract: Based on power on of an electronic device, a location of first data in a NAND flash memory of an electronic device is determined. The first data is transmitted to a shadow RAM of the electronic device, outputting the first data is output from the shadow RAM to a host device of the electronic device through a serial peripheral interface (SPI) when accessing the location of the first data in the NAND Flash memory.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Applicant: Macronix International Co., Ltd.
    Inventor: Chun-Lien Su
  • Patent number: 11640308
    Abstract: Based on power on of an electronic device, a location of first data in a NAND flash memory of an electronic device is determined. The first data is transmitted to a shadow RAM of the electronic device, outputting the first data is output from the shadow RAM to a host device of the electronic device through a serial peripheral interface (SPI) when accessing the location of the first data in the NAND Flash memory.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: May 2, 2023
    Assignee: Macronix International Co., Ltd.
    Inventor: Chun-Lien Su
  • Publication number: 20230004649
    Abstract: A method provides the capability to maintain integrity of a data image stored by computing a hash value (“digest”) of the data image and comparing the hash value computed for the data image with a hash value computed for the data image and kept in a non-volatile area of memory. Bit flips in the data image that are a result of memory hardware errors reveal themselves as differences in the digest computed for the data image and the computed digest for the data.
    Type: Application
    Filed: July 1, 2021
    Publication date: January 5, 2023
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chun-Lien SU
  • Publication number: 20220392562
    Abstract: The disclosed technology provides for automatically skipping bad block(s) in continuous read or sequential read operations in memory devices including NAND flash memory. Bad blocks can be skipped by analyzing block integrity during one at a time addressing of the blocks, or by skipping sets of consecutive bad blocks in a set of bad blocks using stored bad block information. Multiple sets of consecutive bad blocks can also be analyzed and skipped. A list of good blocks can be maintained, and only good blocks are used when performing a continuous cache read or sequential read operation. The list can be maintained in non-volatile memory enabling the device to load the block addresses upon power on startup. Additionally, a command to add additional blocks when received can implement adding new blocks to the list.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 8, 2022
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan HUNG, Chun-Lien SU
  • Patent number: 11500775
    Abstract: A memory system stores user data including file content in clusters of memory space, folder entries, metadata, and a file allocation table FAT including FAT entries. The system comprises a cache memory, an addressable memory including memory space, and control logic coupled to the addressable memory and the cache memory. The control logic is configured to store user data in a current cluster at a current cluster offset including file content, and corresponding metadata including the current cluster offset, and a linked cluster offset of a linked cluster linking to the current cluster in the addressable memory, and to cache a FAT entry pointing to the current cluster in the cache memory.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: November 15, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chun-Lien Su
  • Patent number: 11487908
    Abstract: A memory controller, which manages a memory device, receives a memory command. The memory controller determines whether the memory command is encrypted. Upon determining that the memory command is encrypted, the memory controller performs a decryption function corresponding to the memory command. Conditioned on the performance of the decryption function resulting in a successful decryption of the memory command, the memory controller performs an operation on a memory location corresponding to a memory address included in the memory command.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: November 1, 2022
    Assignee: Macronix International Co., Ltd.
    Inventor: Chun-Lien Su
  • Patent number: 11468963
    Abstract: A memory device and a read method thereof are provided. The read method of the memory cell array includes: reading a memory cell array to obtain page data; dividing the page data into a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequence to respectively generate a plurality of first corrected chunk data; performing a second error correction operation on the page data to generate corrected page data; and outputting the corrected chunk data by referring to an indicating signal.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: October 11, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chun-Lien Su
  • Patent number: 11455254
    Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 27, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Lien Su, Chun-Hsiung Hung, Shuo-Nan Hung
  • Publication number: 20220283738
    Abstract: A flash memory and a writing method thereof are provided. The flash memory includes a plurality of memory blocks and a plurality of multiplex circuits. The memory blocks are arranged into a plurality of memory banks. Each of the memory blocks transmits a plurality of erase voltages or a plurality of program voltages to the corresponding memory bank for executing an erase operation or a program operation. The program operation is executed by one of the memory banks while the erase operation is executed by another one of the memory banks according to a programming while erasing instruction.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chun-Lien Su, Chang-Ting Chen
  • Publication number: 20220269606
    Abstract: A memory system stores user data including file content in clusters of memory space, folder entries, metadata, and a file allocation table FAT including FAT entries. The system comprises a cache memory, an addressable memory including memory space, and control logic coupled to the addressable memory and the cache memory. The control logic is configured to store user data in a current cluster at a current cluster offset including file content, and corresponding metadata including the current cluster offset, and a linked cluster offset of a linked cluster linking to the current cluster in the addressable memory, and to cache a FAT entry pointing to the current cluster in the cache memory.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chun-Lien SU
  • Publication number: 20220269513
    Abstract: Based on power on of an electronic device, a location of first data in a NAND flash memory of an electronic device is determined. The first data is transmitted to a shadow RAM of the electronic device, outputting the first data is output from the shadow RAM to a host device of the electronic device through a serial peripheral interface (SPI) when accessing the location of the first data in the NAND Flash memory.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 25, 2022
    Applicant: Macronix International Co., Ltd.
    Inventor: Chun-Lien Su
  • Publication number: 20220188238
    Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chun-Lien Su, Chun-Hsiung Hung, Shuo-Nan Hung
  • Publication number: 20220180961
    Abstract: A memory device and a read method thereof are provided. The read method of the memory cell array includes: reading a memory cell array to obtain page data; dividing the page data into a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequence to respectively generate a plurality of first corrected chunk data; performing a second error correction operation on the page data to generate corrected page data; and outputting the corrected chunk data by referring to an indicating signal.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 9, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventor: Chun-Lien Su
  • Publication number: 20220138109
    Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan HUNG, Chun-Lien SU
  • Patent number: 11249913
    Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: February 15, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan Hung, Chun-Lien Su
  • Patent number: 11209985
    Abstract: An input/output delay optimization method, used in an electronic system comprising a host controller and a memory device. The method comprising: switching the memory device from a first mode to a second mode a high power consumption mode of the memory device; transmitting one or more first read commands to the memory device, wherein the one or more first read commands are transmitted according to different output delay values; determining an optimized output delay value according to the response status of memory device for the one or more first read commands; transmitting one or more second read commands to the memory device, wherein the one or more second read commands are transmitted according to the optimized output delay value; receiving a known data from the memory device according to different input delay values; and determining an optimized input delay value according to the correctness of the received known data.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: December 28, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Sheng-Lun Wu, Chun-Lien Su, Zong-Qi Zhou
  • Patent number: 11182302
    Abstract: A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 23, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Lien Su, Shuo-Nan Hung, Chun-Hsiung Hung