Abstract: A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.

Abstract: A system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory blocks. The controller is configured to perform at least one wear leveling operation, based on at least one degradation curve, to at least one of the plurality of memory blocks. Furthermore, a method associated with wear leveling is also disclosed herein.

Abstract: A system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory blocks. The controller is configured to perform at least one wear leveling operation, based on at least one degradation curve, to at least one of the plurality of memory blocks. Furthermore, a method associated with wear leveling is also disclosed herein.

Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.

Abstract: A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.

Abstract: A non-volatile register is provided. The non-volatile register includes a plurality of cell strings with respect to a plurality of bit lines, wherein each cell string includes a plurality of cells. Each word line is respectively connecting to a gate of one cell for each cell string to correspondingly form a page. The pages are configured into: a central page used as a register to store registered data; and a plurality of dummy pages at both sides of the central page. The dummy pages are controlled to provide a boosted channel voltage to a portion of memory cells of the central page, not being programmed. A source selection transistor is connected to a first side for each cell string. A drain selection transistor is connected to a second side for each cell string.

Abstract: Systems, devices, and methods for data transfer between memory devices on a shared bus are provided. In one aspect, a system includes first and second memory devices and a shared bus. A host device is configured to send at least one control signal through the shared bus to the first and second memory devices, and the control signal specifies data to be transferred from the first memory device to the second memory device. In response to receiving the control signal, the first memory device is configured to read and transmit the data to the shared bus, and the second memory device is configured to receive the data from the shared bus and write the data in the second memory device. The data is transferred directly from the first memory device to the second memory device through the shared bus without passing through the host device.

Abstract: A memory controller, which manages a memory device, receives a memory command. The memory controller determines whether the memory command is encrypted. Upon determining that the memory command is encrypted, the memory controller performs a decryption function corresponding to the memory command. Conditioned on the performance of the decryption function resulting in a successful decryption of the memory command, the memory controller performs an operation on a memory location corresponding to a memory address included in the memory command.

Abstract: A host device receives, from a memory device, secure data that includes a first content block and a second content block. Upon determining that the first content block is encrypted, the host device decrypts the first content block to obtain corresponding first plaintext data. Upon determining that the second content block is unencrypted, the host device obtains corresponding second plaintext data from the second content block. When the reception of secure data from the memory device is completed, the host device obtains a first signature from a signature block sent along with the secure data. The host device computes a second signature on the plaintext data obtained by the host device, and compares the first signature to the second signature. If the host device determines that the first signature is equal to the second signature, then the host device accepts the plaintext data as legitimate.

Abstract: A memory device, an electronic device, and associated read method are provided. The electronic device includes the memory device and a host device, which are electrically connected to each other. The memory device includes a NAND flash memory and a control logic. The NAND flash memory includes a first physical page, and the first physical page includes a plurality of first acquisition-units. The control logic is electrically connected to the NAND flash memory. The control logic receives a first-page address corresponding to the first physical page from a host device during a first page-read duration. Data stored at the plurality of first acquisition-units are respectively transferred to the host device during a second page-read duration.

Abstract: Systems, devices, and methods for data transfer between memory devices on a shared bus are provided. In one aspect, a system includes first and second memory devices and a shared bus. A host device is configured to send at least one control signal through the shared bus to the first and second memory devices, and the control signal specifies data to be transferred from the first memory device to the second memory device. In response to receiving the control signal, the first memory device is configured to read and transmit the data to the shared bus, and the second memory device is configured to receive the data from the shared bus and write the data in the second memory device. The data is transferred directly from the first memory device to the second memory device through the shared bus without passing through the host device.

Abstract: An input/output delay optimization method, used in an electronic system comprising a host controller and a memory device. The method comprising: switching the memory device from a first mode to a second mode a high power consumption mode of the memory device; transmitting one or more first read commands to the memory device, wherein the one or more first read commands are transmitted according to different output delay values; determining an optimized output delay value according to the response status of memory device for the one or more first read commands; transmitting one or more second read commands to the memory device, wherein the one or more second read commands are transmitted according to the optimized output delay value; receiving a known data from the memory device according to different input delay values; and determining an optimized input delay value according to the correctness of the received known data.

Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.

Abstract: A semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions, wherein each of the diffusion regions comprise source and drain regions of a bit line transistor pair comprising a first bit line transistor and a second bit line transistor and a plurality of bit line transistor gate pairs in contact with the respective diffusion region pairs, wherein the first bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of a first bit line transistor of the first diffusion region and the first bit lite transistor of the second diffusion region, wherein a second bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of the second bit line transistor of the first diffusion region and the second bit line transistor of the second diffusion layer.

Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively.

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a gate dielectric layer, a floating gate, a control gate, an inter-gate dielectric structure and two doped regions. The gate dielectric layer is disposed on a substrate. The floating gate is disposed on the gate dielectric layer. The control gate is disposed on the floating gate. The inter-gate dielectric structure is disposed between the control gate and the floating gate. The inter-gate dielectric structure includes a first oxide layer, a second oxide layer and a charged nitride layer. The first oxide layer is disposed on the floating gate. The second oxide layer is disposed on the first oxide layer. The charged nitride layer is disposed between the first oxide layer and the second oxide layer. The doped regions are disposed in the substrate at two sides of the floating gate, respectively.

Abstract: A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.