Patents by Inventor Chun-Lien Su
Chun-Lien Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7400011Abstract: A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.Type: GrantFiled: March 6, 2007Date of Patent: July 15, 2008Assignee: Macronix International Co. LtdInventors: Uway Tseng, Wenpin Lu, Chun-Lien Su
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Publication number: 20070269947Abstract: A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Inventors: Kuei-Yun Chen, Chun-Lien Su, Yin-Jen Chen, Ming-Shang Chen
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Publication number: 20070155100Abstract: A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.Type: ApplicationFiled: March 6, 2007Publication date: July 5, 2007Inventors: Uway Tseng, Wenpin Lu, Chun-Lien Su
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Patent number: 7199007Abstract: A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.Type: GrantFiled: March 22, 2004Date of Patent: April 3, 2007Assignee: Macronix International Co., Ltd.Inventors: Uway Tseng, Wenpin Lu, Chun-Lien Su
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Publication number: 20040229437Abstract: A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.Type: ApplicationFiled: March 22, 2004Publication date: November 18, 2004Inventors: Uway Tseng, Wenpin Liu, Chun-Lien Su
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Patent number: 6812149Abstract: A method of forming junction isolation to isolate active elements. A substrate having a plurality of active areas and an isolation area between active areas is provided. A first gate structure is formed on part of the substrate located in the active areas and, simultaneously, a second gate structure serving as a dummy gate structure is formed on the substrate located in the isolation area. A first doped region is formed in the substrate located at two sides of the first and the second gate structures. A bottom anti-reflection layer is formed on the substrate, the first gate structure and the second gate structure. Part of the bottom anti-reflection layer is etched to expose the second gate structure. The second gate structure is removed to expose the substrate. A second doped region serving as a junction isolation region is formed in the substrate located in the isolation area.Type: GrantFiled: September 16, 2003Date of Patent: November 2, 2004Assignee: Macronix International Co., Ltd.Inventors: Chun Chi Wang, Chun Lien Su, Wen Pin Lu
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Patent number: 6723646Abstract: The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.Type: GrantFiled: January 25, 2002Date of Patent: April 20, 2004Assignee: Macronix International Co., Ltd.Inventors: Chun-Lien Su, Chi-Yuan Chin, Shih-Keng Cho, Ming-Shang Chen, Yih-Shi Lin
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Patent number: 6680256Abstract: A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern are partially etched by a sputtering etch technology. In this etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.Type: GrantFiled: June 14, 2001Date of Patent: January 20, 2004Assignee: Macronix International, Co., Ltd.Inventors: Hung-Yu Chiu, Chun-Lien Su, Wen-Pin Lu
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Patent number: 6677211Abstract: A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon nitride in two steps. A tilted ion implantation step is performed to implant nitrogen ions into the polysilicon residue to rich nitrogen containing of the polysilicon residue. A nitrogen anneal step is subsequently performed to completely convert the rich nitrogen containing polysilicon residue into silicon nitride that can eliminate the conductivity of the polysilicon residue and prevent conventional oxygen encroachment occurring.Type: GrantFiled: January 14, 2002Date of Patent: January 13, 2004Assignee: Macronix International Co., Ltd.Inventors: Chun-Lien Su, Chun-Chi Wang, Ming-Shang Chen
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Patent number: 6642118Abstract: A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of the polysilicon residue. An oxygen anneal step is subsequently performed to completely convert the rich oxygen containing polysilicon residue into silicon dioxide that can eliminate the conductivity of the polysilicon residue and prevent oxygen encroachment occurring.Type: GrantFiled: January 14, 2002Date of Patent: November 4, 2003Assignee: Mactronix International Co., Ltd.Inventors: Chun-Lien Su, Chun-Chi Wang, Ming-Shang Chen
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Patent number: 6620714Abstract: A method for reducing oxidation encroachment of stacked gate layer is provided by forming a silicon oxynitride layer on the sidewall surface of the stacked gate layer. A tilted ion implantation step is performed to implant nitrogen ions into the sidewall surface of the stacked gate layer to rich nitrogen containing in the sidewall surface of the stacked gate layer. An oxygen-annealing step is subsequently performed to form a silicon oxynitride layer on the sidewall surface of the stacked gate layer. The silicon oxynitride layer can prevent the polysilicon layer in the stacked gate layer being continuously encroached from the oxygen.Type: GrantFiled: January 14, 2002Date of Patent: September 16, 2003Assignee: Macronix International Co., Ltd.Inventors: Chun-Lien Su, Chun-Chi Wang, Ming-Shang Chen
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Publication number: 20030143850Abstract: The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.Type: ApplicationFiled: January 25, 2002Publication date: July 31, 2003Applicant: Macronix International Co., Ltd.,Inventors: Chun-Lien Su, Chi-Yuan Chin, Shih-Keng Cho, Ming-Shang Chen, Yih-Shi Lin
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Publication number: 20030143789Abstract: A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of the polysilicon residue. An oxygen anneal step is subsequently performed to completely convert the rich oxygen containing polysilicon residue into silicon dioxide that can eliminate the conductivity of the polysilicon residue and prevent oxygen encroachment occurring.Type: ApplicationFiled: January 14, 2002Publication date: July 31, 2003Applicant: Macronix International Co., Ltd.Inventors: Chun-Lien Su, Chun-Chi Wang, Ming-Shang Chen
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Publication number: 20030134471Abstract: A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon nitride in two steps. A tilted ion implantation step is performed to implant nitrogen ions into the polysilicon residue to rich nitrogen containing of the polysilicon residue. A nitrogen anneal step is subsequently performed to completely convert the rich nitrogen containing polysilicon residue into silicon nitride that can eliminate the conductivity of the polysilicon residue and prevent conventional oxygen encroachment occurring.Type: ApplicationFiled: January 14, 2002Publication date: July 17, 2003Applicant: Macronix International Co., Ltd.Inventors: Chun-Lien Su, Chun-Chi Wang, Ming-Shang Chen
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Publication number: 20030134461Abstract: A method for reducing oxidation encroachment of stacked gate layer is provided by forming a silicon oxynitride layer on the sidewall surface of the stacked gate layer. A tilted ion implantation step is performed to implant nitrogen ions into the sidewall surface of the stacked gate layer to rich nitrogen containing in the sidewall surface of the stacked gate layer. An oxygen-annealing step is subsequently performed to form a silicon oxynitride layer on the sidewall surface of the stacked gate layer. The silicon oxynitride layer can prevent the polysilicon layer in the stacked gate layer being continuously encroached from the oxygen.Type: ApplicationFiled: January 14, 2002Publication date: July 17, 2003Applicant: Macronix International Co., Ltd.Inventors: Chun-Lien Su, Chun-Chi Wang, Ming-Shang Chen
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Patent number: 6569735Abstract: A logic/flash memory manufacturing process generates recesses used for isolation in a self-aligned silicide process, in some specific location in the substrate, to avoid short circuits. The problem caused by misaligned borderless contact is avoided. Moreover, Very Large Scale Integration (VLSI) structure integration is improved without extra mask layers.Type: GrantFiled: March 20, 2001Date of Patent: May 27, 2003Assignee: Macronix International Co., Ltd.Inventor: Chun-Lien Su
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Patent number: 6552360Abstract: A method and a circuit layout on a substrate of a semiconductor wafer, suitable for reducing defects during a chemical mechanical polishing process. On the substrate, the circuit layout comprises a plurality of strips of first circuit structure and at least two strips of second circuit structure located on the substrate. Each of the strips of second circuit structure respectively links the front end and the rear end of the plurality of strips of the first circuit structure for the purpose of averaging polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during the chemical mechanical polishing process for reducing defects.Type: GrantFiled: January 25, 2002Date of Patent: April 22, 2003Assignee: Macronix International Co., Ltd.Inventors: Chun-Lien Su, Chi-Yuan Chin, Ming-Shang Chen, Tsung-Hsien Wu, Yih-Shi Lin
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Patent number: 6521518Abstract: A method of eliminating weakness caused by high-density plasma (HDP) dielectric layer is provided. Before forming the HDP dielectric layer, a hot thermal oxide (HTO) layer is previously formed on the semiconductor substrate to serve as a buffer layer. The HTO layer eliminates the defect between the HDP dielectric layer and a cap nitride layer and releases the stress therebetween, and thereby preventing bit line leakage issue.Type: GrantFiled: September 4, 2001Date of Patent: February 18, 2003Assignee: Macronix International Co., Ltd.Inventors: Hung-Yu Chiu, Chun-Lien Su, Wen-Pin Lu
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Publication number: 20020168861Abstract: A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern is partially etched by a sputtering etch technology. In this etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.Type: ApplicationFiled: June 14, 2001Publication date: November 14, 2002Inventors: Hung-Yu Chiu, Chun-Lien Su, Wen-Pin Lu
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Publication number: 20020162571Abstract: The present invention provides a planar clean method applicable to shallow trench isolation (STI) for cleaning a substrate having a STI region formed thereon and a high density plasma (HDP) oxide on the surface of the STI region. A buffer oxide etch cleaning solution is exploited and matched by a planar clean way to let the oxide losses of the surface of the silicon substrate and the STI corners match the height and shape of the HDP oxide in the STI region. Thereby, the phenomenon of wrap rounding at the STI corners, which influences growth of the next thermal oxide, can be avoided. The present invention can prevent the STI corners from generating parasitic device characteristics and enhance electric characteristics of the device.Type: ApplicationFiled: May 2, 2001Publication date: November 7, 2002Inventors: Chun Lien Su, Chun Chi Wang, Gen Da You