Patents by Inventor Chun-Lin Tsai
Chun-Lin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8704279Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: GrantFiled: May 25, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8697505Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.Type: GrantFiled: September 15, 2011Date of Patent: April 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chih Chen, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8680616Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.Type: GrantFiled: December 3, 2010Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Chih-Chang Cheng, Ruey-Hsin Liu
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Patent number: 8664741Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.Type: GrantFiled: June 14, 2011Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
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Publication number: 20140054695Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.Type: ApplicationFiled: November 8, 2013Publication date: February 27, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Chih-Chang Cheng, Ruey-Hsin Liu
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Publication number: 20140054708Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.Type: ApplicationFiled: November 4, 2013Publication date: February 27, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20140057407Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.Type: ApplicationFiled: November 7, 2013Publication date: February 27, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20140035035Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: ApplicationFiled: October 11, 2013Publication date: February 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ker Hsiao HUO, Chih-Chang CHENG, Ru-Yi SU, Jen-Hao YEH, Fu-Chih YANG, Chun Lin TSAI
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Publication number: 20140021560Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Jen-Hao Yeh, Chun-Wei Hsu
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Patent number: 8629026Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.Type: GrantFiled: November 12, 2010Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
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Patent number: 8629513Abstract: A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.Type: GrantFiled: January 14, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun-Lin Tsai, Ker Hsiao Huo, Chih-Chang Cheng, Ruey-Hsin Liu
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Patent number: 8624322Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.Type: GrantFiled: July 17, 2012Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Jen-Hao Yeh, Chun-Wei Hsu
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Patent number: 8598679Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.Type: GrantFiled: November 30, 2010Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20130313617Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: ApplicationFiled: May 25, 2012Publication date: November 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8587073Abstract: Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.Type: GrantFiled: October 15, 2010Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen (Albert) Yao, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8575694Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: GrantFiled: February 13, 2012Date of Patent: November 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20130256679Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Wei YAO, Chen-Ju YU, King-Yuen WONG, Chun-Wei HSU, Jiun-Lei Jerry YU, Fu-Chih YANG, Chun Lin TSAI
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Publication number: 20130207187Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: ApplicationFiled: February 13, 2012Publication date: August 15, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ker Hsiao HUO, Chih-Chang CHENG, Ru-Yi SU, Jen-Hao YEH, Fu-Chih YANG, Chun Lin TSAI
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Patent number: 8507920Abstract: An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.Type: GrantFiled: July 11, 2011Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chih Chen, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8502326Abstract: An integrated circuit structure includes a semiconductor substrate and a high-voltage metal-oxide-semiconductor (HVMOS) device, which includes a first high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate; a drain region of a second conductivity type opposite the first conductivity type in the semiconductor substrate and spaced apart from the first HVW region; a gate dielectric with at least a portion directly over the first HVW region; and a gate electrode over the gate dielectric. The gate dielectric includes a bottom gate oxide region; and a silicon nitride region over the bottom gate oxide region.Type: GrantFiled: September 22, 2010Date of Patent: August 6, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Jiun-Lei Jerry Yu, Chien-Chih Chou, Chun-Lin Tsai