Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor structure includes a substrate, a first active region, a second active region and a third active region over the substrate, a first gate structure over a channel region of the first active region, a second gate structure over a channel region of the second active region, a third gate structure over a channel region of the third active region, a first cap layer over the first gate structure, a second cap layer over the second gate structure, and a third cap layer over the third gate structure. A height of the second gate structure is smaller than a height of the first gate structure or a height of the third gate structure.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a substrate, a first doped region disposed in the substrate and doped with a first doping polarity, and a second doped region disposed in the substrate and horizontally outside the first doped region. The second doped region is doped with a second doping polarity opposite to the first doping polarity. The semiconductor device further includes a third doped region disposed completely within the first doped region. The third doped region is doped with the second doping polarity. The semiconductor device further includes a first isolation structure disposed over the first doped region and spaced apart from the second doped region and the third doped region, a second isolation structure disposed over the first doped region and the third doped region, and a resistor disposed over the first isolation structure.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes an active region having a channel region and a source/drain region, a gate structure over the channel region, a gate spacer layer disposed over the channel region and extending along a sidewall of the gate structure, an epitaxial source/drain feature over the source/drain region, a contact etch stop layer (CESL) disposed on the epitaxial source/drain feature and extending along a sidewall of the gate spacer layer, a source/drain contact disposed over the epitaxial source/drain feature, and a dielectric cap layer disposed over the gate structure, the gate spacer layer and at least a portion of the CESL. A sidewall of the source/drain contact is in direct contact with a sidewall of the CESL.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) semiconductor structure for wide-bandgap semiconductor devices in which the wide-bandgap semiconductor devices are split amongst a first IC die and a second IC die. The first IC die includes a first substrate and a first semiconductor device. The first substrate includes a first wide-bandgap material, and the first semiconductor device overlies the first substrate and is formed in part by the first wide-bandgap material. The second IC die overlies the first IC die and is bonded to the first IC die by a bond structure between the first and second IC dies. Further, the second IC die includes a second substrate and a second semiconductor device. The second substrate includes a second wide-bandgap material, and the second semiconductor device underlies the second substrate and is formed in part by the second wide-bandgap material.

Abstract: Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source/drain features in the first and second recesses, respectively.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: A solar panel bracket with a water conducting function for carrying a plurality of solar photovoltaic panels, comprising: a plurality of first brackets, each of the first brackets is arranged in parallel with each other, each of the first brackets has a first water conducting groove; a plurality of second brackets, each of the second brackets is arranged in parallel with each other, each of the second brackets has a second water conducting groove, the second brackets and the first brackets are arranged perpendicular to each other, and the second brackets and the first brackets surround to form a plurality of square spaces, the solar photovoltaic panels are arranged on the square spaces; and a plurality of third water conducting groove groups, each of the third water conducting groove groups is disposed on the side of each of the first brackets, and each of the third water conducting groove group has a third water conducting groove, and the second water conducting grooves communicate with the third water condu

Abstract: A signal transmitter includes a plurality of driver slices. Each of the driver slices includes a driving circuit, a plurality of first transistors, and a plurality of second transistors. The driving circuit receives an input signal and outputting an output signal. The first transistors provide a first impedance according to signals on gate terminals of the first transistors. The second transistors provide a second impedance according to signals on gate terminals of the second transistors. Each of the gate terminals of the first transistors and the second transistors is selectively coupled to a bias voltage which controls the corresponding first transistor or second transistor to operate in a triode region, or coupled to a predetermined voltage which controls the corresponding first transistor or second transistor to behave as a switch.

Abstract: An antenna system with switchable radiation gain includes a signal feeding element, a first antenna element, a second antenna element, a first diode, a first switch element, a second switch element, a first impedance transformer, and a second impedance transformer. The first antenna element is coupled to a first connection point. The second antenna element is coupled to a second connection point. The first diode has an anode coupled to the first connection point, and a cathode coupled to the second connection point. The first switch element and the second switch element are configured to select either the first impedance transformer or the second impedance transformer as a first target transformer, and the selected first target transformer is coupled between the first connection point and the signal feeding element.

Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material.

Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.

Abstract: A compound having a structure of Formula I is disclosed, where at least one of R1 and R2 that is ortho to a boron atom of Formula I comprises a structure selected from (9-carbazolyl)-carbazole, indolocarbazole, triphenylene, fluorene, dibenzothiophene, dibenzofuran, dibenzoselenophene, pyridine, pyrimidine, triazine, aza-triphenylene, aza-fluorene, aza-carbazole, aza-dibenzothiophene, aza-dibenzofuran, and aza-dibenzoselenophene.

Abstract: Automation of the comparison of the colors of small surfaces of products. In one embodiment, color differences are measured rather than an absolute color value. An apparatus is provided for capturing color images of a portion of a product or part to provide a sample product image. The sample image is compared to an image of a standard product obtained under the same conditions with the same apparatus. The color difference is measured to determine when it is in a predetermined range.

Abstract: A compound including a first ligand LA of is disclosed. In the structure of Formula I, one of L1 and L2 is C, and the other is N; Y1 to Y14 are each C or N; at least two adjacent Y7, Y8, Y9, and Y10 are carbon atoms that are fused to a structure of Z1 and Z2 are each O, S, Se, NR, CRR?, or SiRR?; and each R, R?, RA, RB, RC, and RD is hydrogen or a substituent; and any two substituents may be joined or fused together to form a ring. In the compound, LA is complexed to a metal M by L1 and L2, and M has an atomic weight greater than 40. Organic light emitting devices and consumer products containing the compounds are also disclosed.

Abstract: Bonding a full-bridge device and an LLC device in a stack, or forming the full-bridge device and the LLC device on a same substrate, rather than connecting the devices, reduces a chip area associated with a power converter including the full-bridge device and the LLC device. Additionally, the full-bridge device and the LLC device consume less power because parasitic inductance and capacitance are reduced. Additionally, raw materials and production time are conserved that would otherwise have been used to connect the full-bridge device and the LLC device (e.g., via wires).

Abstract: An apparatus for manufacturing semiconductors includes a power amplifier to power a laser, a catalyst disposed in the power amplifier, an inlet port, and an exhaust port. The inlet port introduces a mixing gas to an interior of the power amplifier during a cleaning operation so that the mixing gas contacts a surface of the catalyst having a build-up thereon. The mixing gas reacts with and removes the build-up by generating gaseous by-products. The exhaust port removes the gaseous by-products from the power amplifier.

Abstract: Provided are compounds capable of functioning as an emitter in an organic light emitting device at room temperature, and their use in OLED related electronic devices.