Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.

Abstract: A transaction merging method for a first electronic device and a second electronic device. The transaction merging method comprises: (a) receiving a plurality of input transactions from the first electronic device; (b) setting a merge condition of the input transactions according to a transmission condition between the first electronic device and the second electronic device; (c) merging the input transactions according to the merge condition to generate at least one transaction group; and (d) transmitting the transaction group to the second electronic device.

Abstract: Embodiments provide a method for forming a semiconductor device structure, includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked thereover, forming a sacrificial gate structure over a portion of the fin structure, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers to expose portions of each of the first semiconductor layers. The method includes surrounding the exposed portions of each of the first semiconductor layers with a cladding layer, wherein the cladding layer is formed of a material chemically different from the first semiconductor layers, and the cladding layer has a first atomic percentage of germanium.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

Abstract: A package structure includes a first and a second conductive feature structures, a die, an insulator, an encapsulant, an adhesive layer, and a first through via. The die is located between the first conductive feature structure and the second conductive feature structure. The die is electrically connected to the second conductive feature structure. The insulator is disposed between the die and the first conductive feature structure. The insulator has a bottom surface in physical contact with a polymer layer of the first conductive feature structure. The encapsulant is located between the first conductive feature structure and the second conductive feature structure. The encapsulant is disposed on the insulator and laterally encapsulates the die and the insulator. The adhesive layer is disposed between the die and the insulator. The first through via extends through the encapsulant to connect to the first conductive feature structure and the second conductive feature structure.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes an S/D contact structure formed over the first S/D structure, and a dielectric wall formed below the gate structure and the S/D contact structure. The dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.

Abstract: New organometallic complexes having bis- or tris-heteroleptic ligands and large aspect ratio in one direction and their use in OLEDs to enhance the efficiency is disclosed.

Abstract: A method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.

Abstract: A heteroleptic compound of Formula Ir(LA)x(LB)y is provided, where LA has Formula I, and a structure of Formula II, is bonded to two adjacent C atoms selected from X1, X2, X3, and X4 by the dashed lines to form a fused ring; and LB is selected from the group consisting of

Abstract: A reconfigurable intelligent surface includes a radiant layer, a sensing feeding circuit layer, a processing layer and a controlling circuit layer. The radiant layer includes at least two antennas and a plurality of reflecting units. Each of the at least two antennas is configured for sensing a polarization, a frequency or a direction angle of an incident electromagnetic wave. The reflecting units are arranged to form a reflecting surface. The sensing feeding circuit layer is signally connected to the antennas. The processing layer is signally connected to the sensing feeding circuit layer, and the processing layer is configured to produce a controlling signal corresponding thereto. The controlling circuit layer is signally connected to the radiant layer and the processing layer, wherein the controlling circuit layer receives the controlling signal and controls the reflecting units according to the controlling signal to adjust and form a reflecting electromagnetic wave.

Abstract: An antenna rotation structure includes a rotating shaft member rotatably disposed through a perforated groove of a housing, an annular member, and an elastic member. The rotating shaft member has a holding portion located in an accommodating space of the housing, a connecting portion connected to the holding portion and with an annular groove, and a gripping portion with one end connected to the connecting portion and the other end protruded from the housing. The annular member is disposed in the annular groove and abuts the perforated groove. The elastic member is sleeved on the one end of the gripping portion. The connecting portion and the one end of the gripping portion are disposed in the perforated groove. The gripping portion is turned to drive the rotating shaft member to rotate, thereby adjusting an angle of the antenna.

Abstract: Antenna rotation structure includes a rotating member and an angle adjusting member. The rotating member is rotatably disposed along an axial direction in an accommodating space of the housing and includes a holding portion and a pushing portion disposed at one side of the holding portion spaced apart from the axial direction. The angle adjusting member includes a pressing portion bonded to a through hole of the housing and made of an elastic material and, an abutting portion connected to the pressing portion and corresponding to the pushing portion. When the pressing portion is pressed by a force, it deforms and drives the abutting portion to push the pushing portion to drive the holding portion to rotate about the axial direction to adjust the angle of the antenna.

Abstract: A luminous panel includes a circuit board, a plurality of connecting pads, a chip and two alignment structures. The connecting pads are located on the circuit board. The chip is located on the circuit board and at least partially covers the connecting pads. The two alignment structures are located on the circuit board. The two alignment structures and the connecting pads are at the same level. The two alignment structures are located at two diagonal corners of the chip. At least one part of the two alignment structures protrudes from the outline of the chip.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

Abstract: A multi-angle adjustable and transformable heat pipe includes a sealed case body. A working fluid is filled in the sealed case body. At least one capillary structure is disposed on an inner wall of the sealed case body. The sealed case body has a front section, a rear section and a transformable flexible middle section. The middle section is positioned between the front section and the rear section in connection therewith. The middle section is composed of multiple support sections and multiple knot sections. The support sections and the knot sections are alternately arranged. Two sides of each knot section are respectively connected with adjacent support sections, whereby the support sections can be adjusted by the same angle or different angles with the knot sections serving as fulcrums so that the heat pipe can be multi-angle adjusted and transformed and located.

Abstract: Disclosed is a method of metrology. The method comprises measuring at least one surrounding observable parameter relating to a surrounding signal contribution to a metrology signal which comprises a contribution to said metrology signal which is not attributable to at least one target being measured and determining a correction from said surrounding signal observable parameter. The correction is used to correct first measurement data relating to measurement of one or more targets using measurement radiation forming a measurement spot on one or more of said one or more targets which is larger than one of said targets.

Abstract: An antenna system includes a signal feeding element, a first antenna element, a second antenna element, a first transmission line, and a second transmission line. The first antenna element is coupled to a first connection point. The second antenna element is coupled to a second connection point. The first transmission line is coupled between the signal feeding element and the first connection point. The second transmission line is coupled between the signal feeding element and the second connection point. The length of the second transmission line is substantially equal to that of the first transmission line. The first antenna element and the second antenna element substantially have opposite polarization directions. Therefore, the radiation pattern of the antenna system can provide a plurality of different gain peaks.

Abstract: Devices and techniques are provided in which an OLED panel is operated in two modes. The first mode operates in a standard way to display an image or video or otherwise illuminate sub-pixels of the panel. In the second mode, some pixels are operated at a lower brightness than in the first mode. The use of multiple modes allows for improved sub-pixel lifetime and reduced sub-pixel and image degradation.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: Structures and methods for the co-optimization of various device types include performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in a first substrate region and a third source/drain recess for a third device in a third substrate region different than the first substrate region. In some embodiments, the method further includes performing a second photolithography and etch process to form a second source/drain recess for a second device in a second substrate region different than the first and third substrate regions. The method further includes forming a first source/drain feature within the first source/drain recess, a second source/drain feature within the second source/drain recess, and a third source/drain feature within the third source/drain recess.