Abstract: A packaging structure is used for carrying at least one carried object. The packaging structure includes a carrying unit and a covering member. The carrying unit includes a supporting plate, at least one first side plate connected to the edge of the supporting plate, and at least one combing member. The supporting plate has two opposite surfaces, and the first side plate is able to bend to one of the surfaces of the supporting plate, so that the carrying unit can be folded or unfolded. The first side plate is stacked on the supporting plate when the carrying unit is in the folded state, and the combing member keeps the first side plate stacked on the supporting plate. The covering member positions the carried object on the carrying unit. A delivering device is provided for clamping and positioning a plurality of the packaging structures in an upright manner.

Abstract: An electronic device, including a host, a main display, an auxiliary display, and a lifting mechanism, is provided. The main display is pivoted to the host. The auxiliary display is disposed on the host. The lifting mechanism is disposed between the auxiliary display and the host. The lifting mechanism is configured to lift the auxiliary display and maintain a lifting height of the auxiliary display.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: A portable electronic device including a first body, a second body, and a hinge mechanism is provided. The second body is connected to the first body through the hinge mechanism, and the hinge mechanism has a basis axis located at the first body and a rotation axis located at a lower end of the second body. When the second body rotates with respect to the first body, the rotation axis slides along an arc shaped path with respect to the basis axis to increase or decrease a distance between the rotation axis and the basis axis and increase or decrease a distance between the lower end of the second body and a back end of the first body.

Abstract: A microbial carrier and a device for treating wastewater are provided. The microbial carrier includes a bacteriophilic material and a plurality of foam cells, wherein the foam cells are disposed in the bacteriophilic material. The bactericidal material is a reaction product of a composite, wherein the composition includes a hydrophobic polyvinyl alcohol and a cross-linking agent, wherein the surface energy of the hydrophobic polyvinyl alcohol is 30 mJ/m2 to 58 mJ/m2.

Abstract: A system for harvesting a tendon graft is disclosed, including a retractor, a guide and a harvesting tool. The retractor is collapsible and upon release, becomes self-supporting to hold open an anatomic space developed in a patient above the tendon. A guide assembles with the retractor to orient a guide shaft along the retractor and thereby the anatomic space. The harvesting tool includes a working end with a blade edge for cutting into the tendon. The harvesting tool defines a contoured surface for engaging and translating along the guide shaft while assembled to the retractor. The guide shaft and contoured surface limit the trajectory and translation extent of the harvesting tool along and into the tendon.

Abstract: A solar cell module is provided. The solar cell module includes a first substrate, a second substrate opposite the first substrate, a cell unit disposed between the first and second substrates, a first thermosetting resin layer disposed between the cell unit and the first substrate, a first thermoplastic resin layer disposed between the cell unit and the first thermosetting resin layer, a second thermosetting resin layer disposed between the cell unit and the second substrate, and a second thermoplastic resin layer disposed between the cell unit and the second thermosetting resin layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

Abstract: A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.

Abstract: Provided is a monoclonal antibody of matrix metalloproteinase 1. The monoclonal antibody has a heavy chain variable region with an amino sequence comprising i) CDR1 selected from the group consisting of SEQ ID NOs: 1, 7 and 13, ii) CDR2 selected from the group consisting of SEQ ID NOs: 2, 8 and 14, and iii) CDR3 selected from the group consisting of SEQ ID NOs: 3, 9 and 15. The monoclonal antibody also has a light chain variable region with an amino sequence comprising i) CDR1 selected from the group consisting of SEQ ID NOs: 4, 10 and 16, ii) CDR2 selected from the group consisting of SEQ ID NOs: to 5, 11 and 17, and iii) CDR3 selected from the group consisting of SEQ ID NOs: 6, 12 and 18. A polynucleotide encoding the monoclonal antibody and a complementary polynucleotide sequence thereof are provided as well. A detection kit and a detection method are also provided, wherein the detection kit contains the monoclonal antibody of the matrix metalloproteinase 1.

Abstract: A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.

Abstract: An electronic device assembly is provided, including an electronic device body and a detachable lens module. The electronic device body has a housing and a first joining unit, wherein the first joining unit is disposed on the housing. The detachable lens module is detachably assembled onto the housing and has a second joining unit, wherein the first joining unit is joined to the second joining unit to electrically connect the detachable lens module to the electronic device body.

Abstract: A semiconductor device includes a conductive line disposed within a dielectric layer, a metal layer disposed over and in direct contact with the conductive line, and a metallization layer disposed over the metal layer such that a protruding segment of the metal layer acts as an interface between the conductive line and the metallization layer. The conductive line is copper (Cu) and the metal layer is ruthenium (Ru). The Ru metal layer includes an upper metal layer section and a lower metal layer section.

Abstract: A hydrophobic polyvinyl alcohol and a method for preparing hydrophobic polyvinyl alcohol are provided. The hydrophobic polyvinyl alcohol includes a first repeat unit represented by Formula (I), a second repeat unit represented by Formula (II), and a third repeat unit represented by Formula (III) wherein R1 is —Si(R2)3, R2 is independently C1-6 alkoxy group, C6-18 alkyl group, or C6-22 alkenyl group, and at least one R2 is C6-18 alkyl group or C6-22 alkenyl group; R3 and R4 are independently C6-18 alkyl group or C6-22 alkenyl group; j is 3 to 7; and k is 1 to 30.

Abstract: A metal shielding frame is provided. The metal shielding frame is adapted to be disposed in a socket, wherein the socket is adapted to be electrically connected to a connector. The metal shielding frame includes a sleeve-shaped frame body and at least one ground hemming portion. The sleeve-shaped frame body includes a first enclosed edge. The ground hemming portion is formed on the first enclosed edge. The socket includes a socket case and a socket joint. The socket case surrounds the socket joint. The sleeve-shaped frame body is adapted to be inserted between the socket case and the socket joint.

Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.

Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

Abstract: The present invention relates to integrated circuits and related method steps for forming an IC chip. The method steps result in semiconductor device structures that include redundant same via level formation using a top via subtractive etch and bottom via from dual damascene etch techniques. In embodiments, the same level redundancy via option is optional. Provision of redundant same via level connections using dual damascene processes improves device resistance and capacitive performance. Further method steps result in semiconductor device structures that include a direct super via connection bypassing subtractive etch metal level via formations. These highlighted method steps increase design flexibility—and reduce device footprint (by skipping a metal level) with the benefit of reduced via connection height and shorter metal connections.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.