Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: Embodiments of the present invention provide computer-implemented methods, computer program products and computer systems. Embodiments of the present invention can, in response to receiving a request, dynamically generate a composite application that includes one or more micro applications based, at least in part, on a user's intention.

Abstract: Embodiments of the present invention provide computer-implemented methods, computer program products and computer systems. Embodiments of the present invention can, in response to receiving a request, dynamically generate a composite application that includes one or more micro applications based, at least in part, on a user's intention.

Abstract: Tunable, broadband directional coupler circuits employing one or more additional, switchable coupling circuits for controlling frequency response, and related methods. In exemplary aspects, the directional coupler includes one or more additional coupling circuits that each include an additional coupling line located adjacent to the primary coupling line and that can be selectively activated to change a frequency response of the directional coupler. When an additional coupling circuit is activated, its additional coupling line has the effect of extending the length of the primary coupling line through mutual inductance, thus changing the coupling frequency response of the directional coupler. The additional coupling circuit includes one or more switch(es) to allow for the selective coupling of its additional coupling line to the coupling and/or isolation ports of the directional coupler to selectively change and control the frequency response of the primary coupling line.

Abstract: The present disclosure provides communication systems and devices for use in noise environments, such as during magnetic resonance imaging (MRI). In some embodiments, a communication headrest is provided that consists of a headrest that supports a patients' head, an optional bone conduction microphone, and one or more vibration actuators. The headset makes contact with noise-isolating earplugs worn by the subject such that vibrations generated by the vibration actuators are transferred through the earplug, via acoustic conduction, to enable the patient to hear audio content while the earplugs provide passive noise protection by occluding the ear canal.

Abstract: A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

Abstract: Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.

Abstract: An integrated circuit has corner regions and non-corner regions between the corner regions and includes a semiconductor substrate, conductive pads, passivation layer, post-passivation layer, first conductive posts, and second conductive posts. The conductive pads are disposed over the semiconductor substrate. The passivation layer and the post-passivation layer are sequentially disposed over the conductive pads. The first conductive posts and the second conductive posts are disposed on the post-passivation layer and are electrically connected to the conductive pads. The first conductive posts are disposed in the corner regions and the second conductive posts are disposed in the non-corner regions. Each of the first conductive posts has a body portion and a protruding portion connected to the body portion. A central axis of the body portion of the first conductive post has an offset from a central axis of the protruding portion of the first conductive post.

Abstract: A semiconductor device including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure and a second connector structure is provided. The first conductive pad is disposed on the semiconductor die, wherein the first conductive pad has a first lateral dimension. The second conductive pad is disposed on the semiconductor die, wherein the second conductive pad has a second lateral dimension. The first connector structure is disposed on the first conductive pad, wherein the first connector structure has a third lateral dimension greater than the first lateral dimension. The second connector structure is disposed on the second conductive pad, wherein the second connector structure has a fourth lateral dimension smaller than the second lateral dimension.

Abstract: A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.

Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer.

Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate, a plurality of inner spacer features interleaving the plurality of nanostructures. The plurality of nanostructures are arranged along a direction perpendicular to the substrate. The plurality of inner spacer features include a bottommost inner spacer feature and upper inner spacer features disposed above the bottommost inner spacer feature. The first height of the bottommost inner spacer feature along the direction is greater than a second height of each of the upper inner spacer features.

Abstract: An LED illumination device for improving anti-surge capability includes a circuit substrate, a bridge rectifier chip, a surge absorber group, a first anti-surge current-limiting chip group, a second anti-surge current-limiting chip group, an LED illuminating group, and an LED current-limiting group. The surge absorber group is disposed on the circuit substrate and electrically connected to the bridge rectifier chip for absorbing a surge voltage. The first anti-surge current-limiting chip group is disposed on the circuit substrate for absorbing a first predetermined surge voltage. The second anti-surge current-limiting chip group is disposed on the circuit substrate for absorbing a second predetermined surge voltage. The LED illuminating group includes a plurality of LED chips disposed on the circuit substrate. The LED current-limiting group is disposed on the circuit substrate for controlling a total harmonic distortion of current (THDi) of the LED illuminating group.

Abstract: Systems and methods are provided for delivering images to a patient before and/or during a medical procedure in which a patient is translated on a table relative to a gantry. In various example embodiments, images are projected to the patient while preserving the projected field size during table motion, thereby potentially reducing patient anxiety by providing a more immersive patient viewing experience. In some example embodiments, the projected field size is maintained by a display system that is secured to the table such that both a projector and a projection screen are fixed relative to the table, and relative to the patient, during translation of the table. In some example embodiments, a reduction in patient anxiety may be achieved by projecting images as virtual images that are perceived by the patient as residing at a depth that lies beyond the confined spatial region in which the patient resides.

Abstract: The present disclosure relates a method of forming an integrated chip structure. The method includes etching a base substrate to form a recess defined by one or more interior surfaces of the base substrate. A doped epitaxial layer is formed along the one or more interior surfaces of the base substrate, and an epitaxial material is formed on horizontally and vertically extending surfaces of the doped epitaxial layer. A first doped photodiode region is formed within the epitaxial material and a second doped photodiode region is formed within the epitaxial material. The first doped photodiode region has a first doping type and the second doped photodiode region has a second doping type.

Abstract: A fan system is used for dissipating heat of an electronic device. The fan system includes a fan, a hollow structure, and a control circuit. Sound waves made by the fan are transmitted to an interior of the hollow structure when the fan is operating. The control circuit is connected to the hollow structure and is configured to control deformation/deformations of the hollow structure according to a state/states of the fan and/or the electronic device, which change a volume of the interior of the hollow structure for making a resonance frequency of the hollow structure being approximate to a rotation speed of the fan or being the same as the rotation speed of the fan.

Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

Abstract: A method for reconstructing a motion track applied to a terminal is provided. The method includes: obtaining a data set, the data set including positioning data obtained by positioning a target object; performing data fitting on target data in the data set to obtain a plurality of segments of first curves, the target data being positioning data obtained by performing noise filtering on the data set; and determining a motion track of the target object based on the plurality of segments of first curves. Counterpart apparatus and non-transitory computer-readable storage medium embodiments are also contemplated.

Abstract: Provided is a bioink comprising a mixture comprising a collagen and a polysaccharide, and a polyhedral oligomeric silsesquioxane (POSS), a hydrogel matrix formed from a bioink comprising a mixture comprising a collagen and a polysaccharide, and a polyhedral oligomeric silsesquioxane (POSS), a 3D biomaterial scaffold comprising a hydrogel matrix of the disclosure as a first hydrogel layer and a hydrogel matrix of the disclosure as a second hydrogel layer, optionally having an intervening layer between the first hydrogel layer and the second hydrogel layer, and methods of forming and using same.