Abstract: Security devices having chaosmetric artifacts from fractal patterns are disclosed. In one aspect, embodiments of the present disclosure include a security device, having a physical surface having formed thereon a composite pattern. The composite pattern can created from created from joining of an imprint of a first base pattern and an imprint of a second base pattern. The first base pattern can be created from a first basic building block. In one embodiment, the first base pattern is a fractal pattern based on the first basic building block which forms chaosmetric artifacts in the physical surface upon printing.

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure includes a fin and a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure over the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed at a bottom of the opening into a seed layer by performing an implantation process; selectively depositing a dielectric layer over the seed layer at the bottom of the opening; and selectively growing a source/drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

Abstract: Systems and methods to perform validation of authentication of a security device in a decentralized network are disclosed. In one aspect, embodiments of the present disclosure include a method which can be implemented on a system to, identify telemetry associated with the successful authentication. The telemetry is further in a distributed ledger in the decentralized network and can be used to determine validity of an authentication attempt of the security device by a second user device.

Abstract: A data flow classification device includes a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit; but if the classification is not found in the lookup table, the forwarding circuit tags the packets with a predetermined classification, outputs the packets to the buffer circuit, and adds the information of the input flow to the lookup table. The configuring circuit determines a flow threshold according to a queue length of the buffer circuit and a target length, learns the traffic of multiple flows from the lookup table, determines the classifications of the multiple flows according to the comparison between the traffic and the flow threshold, and stores these classifications in the lookup table.

Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.

Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.

Abstract: Security devices of various form factors with chaosmetric artifacts are disclosed. In one aspect, embodiments of the present disclosure include a security device, having a physical surface having formed thereon a composite pattern. The composite pattern can created from joining or overlap of imprinting of a first base pattern and a second base pattern. The first base pattern is created from a first basic building block and the basic building block can forms chaosmetric artifacts in the physical surface upon printing.

Abstract: The present invention relates to rice grain with thickened aleurone. Also provided is a rice plant comprising at least one genetic variation which reduces the activity of at least one ROS1a gene in the plant. Grain of the invention, or aleurone there-from, has improved nutritional properties, and hence is particularly useful for human and animal feed products.

Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, recesses, a passivation layer and an etch mask layer. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recesses are disposed in the group III-V barrier layer in the active region and the isolation region, respectively. The passivation layer disposed in the recesses of the active region and the isolation region. The etch mask layer disposed between the passivation layer and the group III-V barrier layer in the active region, where the etch mask layer is spaced apart from bottoms of the recesses in the active region and the isolation region.

Abstract: A carrier structure having a strengthening layer is provided. The strengthening layer comprises 5 to 30% by weight polysiloxane, 1 to 20% by weight silicon dioxide, and 60 to 85% by weight polyethylene terephthalate (PET) film. The carrier structure is used in a semiconductor packaging process for improving the process reliability.

Abstract: A dimmable lamp tube is provided, which includes a first lamp head, a second lamp head and a lamp tube body. The first lamp head has a brightness adjustment switch. The second lamp head has a power adjustment switch. The lamp tube body includes a circuit board and a plurality of light-emitting elements. The light-emitting elements are disposed on the circuit board. The circuit board includes a brightness adjustment switch connection terminal and a power adjustment switch connection terminal. The brightness adjustment switch is connected to the brightness adjustment switch connection terminal and the power adjustment switch is connected to the power adjustment switch connection terminal.

Abstract: A dimmable lamp tube is provided, which includes a first lamp head, a second lamp head and a lamp tube body. The first lamp head has a brightness adjustment switch. The second lamp head has a power adjustment switch. The lamp tube body includes a circuit board and a plurality of light-emitting elements. The light-emitting elements are disposed on the circuit board. The circuit board includes a brightness adjustment switch connection terminal and a power adjustment switch connection terminal. The brightness adjustment switch is connected to the brightness adjustment switch connection terminal and the power adjustment switch is connected to the power adjustment switch connection terminal.

Abstract: A server device includes a casing, an electronic assembly, a cover, and a heat dissipation device. The electronic assembly includes a circuit board and at least one heat source. The circuit board is disposed on the casing, and the heat source is disposed on the circuit board. The cover is slidably disposed on the casing. The heat dissipation device includes at least one air cooling heat exchanger and at least one liquid cooling heat exchanger. The air cooling heat exchanger is fixed on and thermally coupled with the heat source. The liquid cooling heat exchanger is fixed on the cover and thermally coupled with the air cooling heat exchanger.

Abstract: A server device includes a casing, an electronic assembly, a cover, and a heat dissipation device. The electronic assembly includes a circuit board and at least one heat source. The circuit board is disposed on the casing, and the heat source is disposed on the circuit board. The cover is removably disposed on the casing. The heat dissipation device includes at least one air cooling heat exchanger and at least one liquid cooling heat exchanger. The air cooling heat exchanger is fixed on and thermally coupled with the heat source. The liquid cooling heat exchanger is fixed on the cover and thermally coupled with the air cooling heat exchanger.

Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.

Abstract: In some example embodiments, there is provided a tag. The tag may include an antenna configured to receive a first radio frequency signal and to reradiate a second radio frequency signal; and an ultrasonic transducer coupled to the antenna, wherein an ultrasound signal received by the ultrasonic transducer causes a variation of at least one property of the ultrasonic transducer, wherein the variation of the at least one property imparts a modulation onto at least a portion of the first radio frequency signal, and wherein the modulated first radio frequency signal is reradiated by the antenna as the second radio frequency signal. Related system, methods, and articles of manufacture are also disclosed.

Abstract: The present disclosure provides a system. The system includes a metrology tool configured to collect overlay errors from a patterned substrate; and a controller module coupled to the metrology tool and configured to generate an overlay compensation from the collected overlay errors, wherein the generating of the overlay compensation includes identifying a portion of the overlay errors as a set of outliers, identifying inside the set of outliers overlay errors not due to reticle effects, thereby creating a set of noise, excluding the set of noise from overlay errors, thereby creating a set of filtered overlay errors, and calculating the overlay compensation based on the set of filtered overlay errors.

Abstract: Techniques to validate authenticity of association of a physical entity with a non-fungible token and/or to create the non-fungible token having a verifiable association with the physical entity are disclosed. In one aspect, embodiments of the present disclosure include a method which can be implemented on a system to verify that a given physical object associated a non-fungible token on a distributed ledger network is an authentic physical object. In one embodiment, the method includes retrieving authentication metadata for a security device generated from initiating authentication of the security device associated with the given physical object. It can be determined whether the authentication metadata for the security device includes an identifier of the non-fungible token.

Abstract: A high-electron mobility transistor includes a substrate, a GaN channel layer over the substrate, an AlGaN layer over the GaN channel layer, a gate recess in the AlGaN layer, a source region and a drain region on opposite sides of the gate recess, a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively, a p-GaN gate layer in and on the gate recess; and a re-grown AlGaN film on the AlGaN layer, on the GaN source layer and the GaN drain layer, and on interior surface of the gate recess.

Abstract: A display apparatus includes a first circuit board and a plurality of first light emitting display units. The first circuit board has a first surface and a first board edge connected to the first surface. The first light emitting display units are disposed on the first surface. Each of the first light emitting display units has a plurality of first pixel areas and includes a first driving circuit layer electrically bonded to the first circuit board and a plurality of first light emitting devices. The first light emitting devices are disposed on one side of the first driving circuit layer away from the first circuit board and are electrically bonded to the first driving circuit layer. At least one of the first light emitting display units has a first side edge parallel to the first board edge. The first board edge is drawn back from the first side edge.