Patents by Inventor Chun On To

Chun On To has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220407787
    Abstract: A method includes capturing first data associated with a first packet flow originating from a first host using a first capture agent deployed at the first host to yield first flow data, capturing second data associated with a second packet flow originating from the first host from a second capture agent deployed on a second host to yield second flow data and comparing the first flow data and the second flow data to yield a difference. When the difference is above a threshold value, the method includes determining that the second packet flow was transmitted by a component that bypassed an operating stack of the first host or a packet capture agent at the device to yield a determination, detecting that hidden network traffic exists, and predicting a malware issue with the first host based on the determination.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 22, 2022
    Inventors: Khawar Deen, Navindra Yadav, Anubhav Gupta, Shashidhar Gandham, Rohit Chandra Prasad, Abhishek Ranjan Singh, Shih-Chun Chang
  • Publication number: 20220406629
    Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.
    Type: Application
    Filed: April 14, 2022
    Publication date: December 22, 2022
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Chun-Liang Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20220403548
    Abstract: Methods for determining suitability of a silicon substrate for epitaxy and/or for determining slip resistance during epitaxy and post-epitaxy thermal treatment are disclosed. The methods involve evaluating different substrates of the epitaxial wafers by imaging the wafer by infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters may be compared to determine which substrates are well-suited for epitaxial and/or post-epi heat treatments.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 22, 2022
    Inventors: Shan-Hui Lin, Chun-Chin Tu, Zheng Lu
  • Publication number: 20220405920
    Abstract: A portable medical education device, medical education platform, and medical education methods are disclosed. The medical education portable device enables a camera to capture a specific picture to generate an image, extracts several features from the image, converts the features into an identification code, and transmits the identification code to the medical education platform. The medical education platform stores several three-dimensional medical models and finds a specific three-dimensional medical model from the three-dimensional medical models according to the identification code, wherein the preset code corresponding to the specific three-dimensional medical model is the same as the identification code.
    Type: Application
    Filed: March 28, 2022
    Publication date: December 22, 2022
    Inventors: Ding-Han WANG, Chun-Yen LU, Ming-Lun HSU, Yi-Chen HSU, Ngoc Trang TRAN THI, Juin-Hong CHERNG, Po-Han WU, Chia-Yu LIN
  • Publication number: 20220406815
    Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: YU-CHIEN CHIU, MENG-HAN LIN, CHUN-FU CHENG, HAN-JONG CHIA, CHUNG-WEI WU, ZHIQIANG WU
  • Publication number: 20220404636
    Abstract: A head mounted display including a first display, a second display, a third display, and an optical element is provided. The first display projects a first image to a first target area. The second display projects a second image to a second target area. The third display projects a third image. The optical element is disposed among the first target area, the second target area, the first display, the second display, and the third display. The optical element transmits the first image to the first target area and the second image to the second target area, and reflects the third image toward the first target area and the second target area.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Applicant: HTC Corporation
    Inventors: Meng-Che Tsai, Kuei-Chun Liu
  • Publication number: 20220404778
    Abstract: An intellectual quality management method is disclosed. A heatmap risk interface is created according to the required data and the parameter configuration which are calculated using a time dependent risk priority number (RPN) equation. An intellectual audit scheduling algorithm is defined via the heatmap risk interface to automatically generate at least one audit plan. An audit program corresponding to the audit plan is performed and a plurality of problem points are selected. Intellectual root cause category recommendation is performed to the questions points. intellectual corrective actions and preventive action recommendations are performed to the problem points according to the intellectual root cause category recommendation to obtain at least one optimum corrective action and at least one preventive action.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 22, 2022
    Inventors: YI-HSIU HUANG, KUANG-HUNG CHIANG, AI-JUN MENG, YU-HSIANG TUNG, MIN-ZHI SHEN, SHYANG-YIH WANG, PO-CHUN CHANG
  • Publication number: 20220408056
    Abstract: The disclosed method includes accessing video content encoded at a specified frame rate, and determining a refresh rate for an electronic display on which the video content is to be presented. The method next includes specifying a time interval for the video content over which frame rate conversion is to be applied to synchronize the video content frame rate with the electronic display refresh rate. The method also includes presenting the video content on the electronic display where the playback speed is adjusted for a first part of the interval. At this adjusted speed, the interval is played back using original video frames and multiple frame duplications. The presenting also adjusts playback speed of a second part of the interval. At the adjusted speed, the interval is played back using the original frames and a different number of frame duplications. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: August 23, 2022
    Publication date: December 22, 2022
    Inventors: Weiguo Zheng, Rex Yik Chun Ching
  • Patent number: 11532495
    Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 20, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wu-Hung Yen, Yi-Hsien Huang, Chun-Tang Lin, Shu-Hua Chen, Shou-Qi Chang
  • Patent number: 11532507
    Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Patent number: 11532751
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Lei-Chun Chou
  • Patent number: 11532586
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first device tier including a first semiconductor substrate having a first plurality of devices. A second semiconductor substrate is formed over the first device tier. A first conductive layer is formed within the second semiconductor substrate, and a second conductive layer is formed within the second semiconductor substrate and over the first conductive layer. The first conductive layer and the second conductive layer have different patterns as viewed from a top-view. A second plurality of devices are formed on the second semiconductor substrate. The first and second conductive layers are configured to electrically couple the first plurality of devices and the second plurality of devices.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Jen Tseng, Wei-Yu Chen, Ting-Wei Chiang, Li-Chun Tien
  • Patent number: 11531524
    Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Chih-Hui Weng, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang, Chia-Hsiang Chen
  • Patent number: 11531263
    Abstract: Some embodiments relate to photomask for mask patterning. The photomask includes a transparent layer comprising quartz, and a molybdenum silicide (MoSi) layer overlying the transparent layer. A first shielding layer overlies the MoSi layer and has a first thickness and a first optical density. A second shielding layer overlies the first shielding layer and has a second thickness and a second optical density. The second thickness is less than one third of the first thickness, and the second optical density is less than one fourth of the first optical density. An overall optical density of the first and second shielding layers is at least 1.8.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 11528946
    Abstract: A cloth mask includes a body, where the body has a piece of copper ion cloth and a piece of zinc oxide antibacterial cloth, the copper ion cloth is woven by a mixture of a first yarn, a second yarn and a copper yarn, the first yarn has a hydrophobicity and a moisture permeability and can form a water-resistant surface, and has a water-repellent effect and is exposed at an inner layer of the copper ion cloth, and the second yarn has a moisture-removing property and can form an antibacterial and moisture-removing surface to be exposed together with the copper yarn on a surface of the copper ion cloth.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: December 20, 2022
    Assignees: DAI LI ER COMPANY
    Inventor: Hsiang-Chun Lin
  • Patent number: 11531223
    Abstract: To prevent arcing discharge of a liquid crystal device. Provided is a liquid crystal device including a liquid crystal layer, a first substrate, a second substrate and an insulating film, wherein the liquid crystal layer is arranged between the first substrate and the second substrate, the first substrate includes electrode 1, the second substrate includes electrode 2, the insulating film is arranged between electrode 1 and electrode 2, and the insulating film is a cured product of a thermosetting polymer composition.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 20, 2022
    Assignee: JNC CORPORATION
    Inventors: Chien Cheng Liu, Yi Cheng Lan, Yi Pin Lee, Ren Lung Chen, Kuie Hua Hsieh, Chun Hung Chiang, Hiroaki Fujita
  • Patent number: 11529712
    Abstract: An apparatus for performing chemical mechanical polish on a wafer includes a polishing head that includes a retaining ring. The polishing head is configured to hold the wafer in the retaining ring. The retaining ring includes a first ring having a first hardness, and a second ring encircled by the first ring, wherein the second ring has a second hardness smaller than the first hardness.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Chien Hou, Ching-Hong Jiang, Kuo-Yin Lin, Ming-Shiuan She, Shen-Nan Lee, Teng-Chun Tsai, Yung-Cheng Lu
  • Patent number: 11533565
    Abstract: A MEMS microphone includes a substrate having an opening, a first diaphragm, a first backplate, a second diaphragm, and a backplate. The first diaphragm faces the opening in the substrate. The first backplate includes multiple accommodating-openings and it is spaced apart from the first diaphragm. The second diaphragm joints the first diaphragm together at multiple locations by pillars passing through the accommodating-openings in the first backplate. The first backplate is located between the first diaphragm and the second diaphragm. The second backplate includes at least one vent hole and it is spaced apart from the second diaphragm. The second diaphragm is located between the first backplate and the second backplate.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Wen-Tuan Lo
  • Patent number: D973211
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: December 20, 2022
    Assignee: Keaworld Pte Ltd.
    Inventor: Bi Chun Neo
  • Patent number: D973212
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: December 20, 2022
    Assignee: Keaworld Pte Ltd.
    Inventor: Bi Chun Neo