Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: A photocatalyst includes a composite fiber having at least two crystalline semi-conductors that provide a heterojunction structure in the composite fiber.

Abstract: The present invention discloses a method for surface-treating a mirror-finish stainless steel workpiece, which comprises steps: dividing the surface of a mirror-finish stainless steel workpiece into different grinding areas according to the depths of the scratches; selecting sand papers respectively having appropriate grit sizes for the grinding areas, and grinding the grinding areas to remove all the scratches; sequentially using three combinations of polishing agents and grinding materials to undertake polishing; and using an abrasive paste and a fourth grinding material to perform mirror-finishing.

Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.

Abstract: A pixel structure on a display panel comprises three sub-pixels where each sub-pixel can be arranged to a first transmissive region and a second transmissive region. The first transmissive region has a first transistor along with a first photo-resistant layer as well as the second transmissive region has a second transistor along with a second photo-resistant layer. The first photo-resistant layer and the second photo-resistant layer of different thickness or area are formed on a color filter. There exists a function relation between data signals received from the first transistor and the second transistor. Using these two data signals and combining the photo-resistant layers of different thickness or area will make each sub-pixel generate new level of brightness in gray scale and increase the number of displaying colors.

Abstract: The present invention discloses a method for surface-treating a mirror-finish stainless steel workpiece, which comprises steps: dividing the surface of a mirror-finish stainless steel workpiece into different grinding areas according to the depths of the scratches; selecting sand papers respectively having appropriate grit sizes for the grinding areas, and grinding the grinding areas to remove all the scratches; sequentially using three combinations of polishing agents and grinding materials to undertake polishing; and using an abrasive paste and a fourth grinding material to perform mirror-finishing.

Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.

Abstract: A transflective LCD device includes an array substrate and a color filter. The substrate includes a plurality gate lines, a plurality of common lines, and a plurality of data lines substantially crossing the gate lines to define a plurality of sub-pixel regions. Each sub-pixel region has a reflective area and a transmissive area. Two of the reflective area of two adjacent sub-pixel regions in the same column are juxtaposed to each other. The color filter has a plurality of sub-pixel regions respectively aligned with the sub-pixel regions of the array substrate. The color filter includes an insulating layer disposed on the reflective area of a respective sub-pixel region. An LC layer is disposed between the array substrate and the color filter.

Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.

Abstract: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.

Abstract: A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.

Abstract: An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.

Abstract: The present invention discloses a method for surface-treating a mirror-finish stainless steel workpiece, which comprises steps: dividing the surface of a mirror-finish stainless steel workpiece into different grinding areas according to the depths of the scratches; selecting sand papers respectively having appropriate grit sizes for the grinding areas, and grinding the grinding areas to remove all the scratches; sequentially using three combinations of polishing agents and grinding materials to undertake polishing; and using an abrasive paste and a fourth grinding material to perform mirror-finishing.

Abstract: A transflective LCD device includes an array substrate and a color filter. The substrate includes a plurality gate lines, a plurality of common lines, and a plurality of data lines substantially crossing the gate lines to define a plurality of sub-pixel regions. Each sub-pixel region has a reflective area and a transmissive area. Two of the reflective area of two adjacent sub-pixel regions in the same column are juxtaposed to each other. The color filter has a plurality of sub-pixel regions respectively aligned with the sub-pixel regions of the array substrate. The color filter includes an insulating layer disposed on the reflective area of a respective sub-pixel region. An LC layer is disposed between the array substrate and the color filter.

Abstract: A transflective LCD device includes an array substrate and a color filter. The substrate includes a plurality gate lines, a plurality of common lines, and a plurality of data lines substantially crossing the gate lines to define a plurality of sub-pixel regions. Each sub-pixel region has a reflective area and a transmissive area. Two of the reflective area of two adjacent sub-pixel regions in the same column are juxtaposed to each other. The color filter has a plurality of sub-pixel regions respectively aligned with the sub-pixel regions of the array substrate. The color filter includes an insulating layer disposed on the reflective area of a respective sub-pixel region. An LC layer is disposed between the array substrate and the color filter.

Abstract: A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a larger height than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

Abstract: An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.