Patents by Inventor Chun Wang

Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935746
    Abstract: As deposited, hard mask thin films have internal stress components which are an artifact of the material, thickness, deposition process of the mask layer as well as of the underlying materials and topography. This internal stress can cause distortion and twisting of the mask layer when it is patterned, especially when sub-micron critical dimensions are being patterned. A stress-compensating process is employed to reduce the impact of this internal stress. Heat treatment can be employed to relax the stress, as an example. In another example, a second mask layer with an opposite internal stress component is employed to offset the internal stress component in the hard mask layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yi Chang, Chunyao Wang
  • Publication number: 20240088901
    Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: PO CHUN LU, SHAO-YU WANG
  • Publication number: 20240083555
    Abstract: A waste collection apparatus for collecting waste in water is provided. The waste collection apparatus includes a floating device and a waste collection device coupled to the floating device. The waste collection device includes a fluid ejection element, and the flow out of the fluid ejection element flows toward a space where waste is collected.
    Type: Application
    Filed: May 12, 2023
    Publication date: March 14, 2024
    Inventors: Wei-Chun LIU, Ching-Fu WANG, Cheng-Che HO, Huan-Fu LIN
  • Publication number: 20240084536
    Abstract: A waste collection apparatus for collecting waste in water is provided. The waste collection apparatus includes a floating device and a waste collection device coupled to the floating device. The floating device includes a plurality of floating units. The waste collection device is coupled to the floating device. Each of the floating units includes a base and a pillar connected to the base, and the density of the base is greater than the density of the pillar.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 14, 2024
    Inventors: Wei-Chun LIU, Ching-Fu WANG, Cheng-Che HO
  • Publication number: 20240085520
    Abstract: A method of processing an interference detected by a first microwave sensor is disclosed. The method comprising the steps of: receiving, by a second microwave sensor, from the first microwave sensor a message comprising a signal feature profile representing the interference detected by the first microwave sensor; matching, by the second microwave sensor, the signal feature profile comprised in the received message with a stored feature profile, the stored feature profile obtained by the second microwave sensor from its own received signal, and determining, by the second microwave sensor, that the interference detected by the first microwave sensor is caused by the second microwave sensor, if the signal feature profile matches the stored feature profile.
    Type: Application
    Filed: January 18, 2022
    Publication date: March 14, 2024
    Inventors: CHUN YANG, JIALONG QIU, ZHIQUAN CHEN, GANG WANG
  • Publication number: 20240084370
    Abstract: The disclosure provides a kit for detecting microsatellite instability and a method therefor. The kit includes a negative control, a plurality of qPCR reaction solutions, a qPCR premix and a sterile enzyme-free water; the plurality of qPCR reaction solutions includes 6 pairs of upstream primers and downstream primers of which the MSI mutation site is amplified, and a reference probe for the internal reference and a detection probe for the mutation site. The difference between the amplification of the gene and the gene at the mutation site of the samples and the negative control is used to detect the microsatellite instability. The method and kit as provided is easy and simple without the need of normal tissues being a control, and the need to open the cap. By doing so, aerosol pollution is avoided and sample supplies are conserved.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 14, 2024
    Inventors: Chun MENG, Jing HONG, Liang GUO, Wenxiao MA, Yiwei HUANG, Xiaodie LIN, Liling XIE, Xiaoya WANG, Qixin LIN
  • Patent number: 11929254
    Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Ming Lung, ChunYao Wang
  • Patent number: 11927392
    Abstract: The present disclosure is directed to a wafer drying system and method that detects airborne molecular contaminants in a drying gas as a feedback parameter for a single wafer or multi-wafer drying process. For example, the system comprises a wafer drying station configured to dispense a drying gas over one or more wafers to dry the one or more wafers, a valve configured to divert the drying gas to a first portion and a second portion, and an exhaust line configured to exhaust the first portion of the drying gas. The system further comprises a detector configured to receive the second portion of the drying gas and to determine a real time property of the second portion of the drying gas, and a control unit configured to control a feedback operation of the wafer drying station based on the real time property of the second portion of the drying gas.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun Hsu, Sheng-Wei Wu, Shu-Yen Wang
  • Patent number: 11929361
    Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 12, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xin-Yong Wang, Li-Chun Tien, Chih-Liang Chen
  • Patent number: 11929333
    Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Chieh-Yen Chen, Che-Wei Hsu
  • Patent number: 11929328
    Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko JangJian, Ting-Chun Wang, Yung-Si Yu
  • Publication number: 20240079409
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyun-De WU, Te-Chih HSIUNG, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU, Peng WANG, Huan-Just LIN
  • Publication number: 20240077479
    Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 7, 2024
    Applicant: DeepBrain Tech. Inc
    Inventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
  • Publication number: 20240079434
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures.
    Type: Application
    Filed: January 5, 2023
    Publication date: March 7, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung, Yu-Chun Chen
  • Publication number: 20240079048
    Abstract: A memory array circuit includes a semiconductor substrate, a bit line, a complementary bit line, and a bit line sense amplifier circuit. The semiconductor substrate has an original surface. The bit line sense amplifier circuit is connected to the bit line and the complementary bit line, and the bit line sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first plurality of transistors to the bit line and the complementary bit line; wherein the first set of connection lines is above the original surface of the semiconductor substrate, and the bit line and the complementary bit line are under the original surface of the semiconductor substrate.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 7, 2024
    Applicant: Invention And Collaboration Laboratory Pte. Ltd.
    Inventors: Chao-Chun Lu, Chun Shiah, Shih-Hsing Wang
  • Publication number: 20240079332
    Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 7, 2024
    Inventors: Chia-Yang Wu, Shiu-Ko JangJian, Ting-Chun Wang, Yung-Si Yu
  • Publication number: 20240079591
    Abstract: An electrode material for an energy storage device including a covalent organic framework includes a plurality of aromatic moieties each linked by at least one thioether linkage. An anode including said electrode material, and an energy storage device having said anode.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 7, 2024
    Inventors: Qichun Zhang, Chun-Sing Lee, Chenchen Wang, Shen Xu
  • Patent number: 11925035
    Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
  • Patent number: 11923210
    Abstract: In an embodiment, a method includes: immersing a wafer in a bath within a cleaning chamber; removing the wafer out of the bath through a solvent and into a gas within the cleaning chamber; determining a parameter value from the gas; and performing remediation within the cleaning chamber in response to determining that the parameter value is beyond a threshold value.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chun Hsu, Shu-Yen Wang, Chui-Ya Peng
  • Patent number: D1017295
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: March 12, 2024
    Assignee: Nonet Inc.
    Inventors: Beico Chiu, Yi-Chun Wang, Xiang-Yi Zhan