Abstract: Apparatuses, systems, and techniques are presented to reduce an amount of data to be transmitted for media content. In at least one embodiment, one or more neural networks are used to generate video and audio information corresponding to one or more people based, at least in part, on at least one image and voice information corresponding to the one or more people.

Abstract: The embodiments of the present disclosure provide an etching method, an air-gap dielectric layer, and a dynamic random-access memory. The etching method is configured to selectively etch a silicon oxide film on a wafer surface that includes the silicon oxide film and a silicon nitride film. In addition, the etching method includes: a surface layer removal process including: etching the silicon oxide film at a first etching rate and removing a surface modification layer covering on the silicon nitride film; and an etching process including: etching the silicon oxide film at a second etching rate. The first etching rate is smaller than the second etching rate. In the etching method according to the present disclosure, through selectively etching the silicon oxide film, a substantial degradation of an etching selectivity ratio of SiO2/SiN caused by the surface modification layer on the wafer surface can be avoided.

Abstract: The present application provides a pixel circuit, a display panel, and a temperature compensation method for a display panel. The display panel includes a plurality of pixel units. At least one of the plurality of pixel units includes: a display layer comprising a light emitting element; and a thermoelectric conversion layer comprising a thermoelectric element having a first terminal and a second terminal, wherein the first terminal is disposed adjacent to the light emitting element and in thermal contact with the light emitting element, and the second terminal is disposed away from the light emitting element. The thermoelectric element has a first signal terminal and a second signal terminal, and is configured to generate a temperature difference voltage signal between the first signal terminal and the second signal terminal according to a temperature difference between the first terminal and the second terminal.

Abstract: An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.

Abstract: Embodiments of the present invention provide a punctured preamble enabling wireless devices to efficiently use a channel (e.g., an 80 or 160 MHz channel) where a primary service is operating. A Wideband Channel Access Mechanism for 20 MHz/80 MHz operating STAs is provided so that a 20 MHz/80 MHz operating STA can dynamically move to a secondary channel to improve wireless performance of the STA. An AP coordinates the operating channel switch of the 20 MHz/80 MHz operating STA. An EHT cooperative multi-band operation can be applied to the preamble punctured PPDU for simultaneous multi-band operation.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.

Abstract: Methods and apparatuses for selectively etching silicon-and-oxygen-containing material relative to silicon-and-nitrogen-containing material by selectively forming a carbon-containing self-assembled monolayer on a silicon-and-nitrogen-containing material relative to a silicon-and-oxygen-containing material are provided herein. Methods are also applicable to selectively etching silicon-and-nitrogen-containing material relative to silicon-and-oxygen-containing material.

Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.

Abstract: A data unit (e.g., a physical layer convergence procedure (PLCP) protocol data unit (PPDU)) is detected at a first wireless device of a basic service set (BSS). The data unit was sent on a channel from a second wireless device of an overlapping basic service set (OBSS). The data unit is wide-bandwidth, occupying both a primary channel and a secondary channel of the wireless network. The first and second wireless devices are within a same spatial reuse group (SRG). The first wireless device stores the channel bandwidth of the data unit and a receive duration time of the data unit. During the receive duration time of the data unit, a SRG OBSS power density threshold is applied on the secondary channels that are within the channel bandwidth of the data unit, instead of applying a non-SRG OBSS power density threshold on those secondary channels.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a plurality of pixel regions disposed within a substrate and respectively comprising a photodiode configured to receive radiation that enters the substrate from a back-side. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions surrounding the photodiode. The BDTI structure extends from the back-side of the substrate to a first depth within the substrate. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel regions overlying the photodiode. The MDTI structure extends from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure is a continuous integral unit having a ring shape.

Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Abstract: A host system coupled to a storage system provides hardware support for command abort. The host system includes a host controller, which detects that a host driver has disabled an enable indicator of a submission queue (SQ). In response to the detection, the host controller stops further fetching from the SQ. The host controller sends all entries that have been fetched from the SQ to the storage device, and sets a status indicator of the SQ to indicate stopped fetching of the SQ.

Abstract: An image capturing optical lens assembly includes five lens elements, in order from an object side to an image side along an optical path, being a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The fourth lens element with positive refractive power has an image-side surface being convex in a paraxial region thereof. The fifth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. At least one of surfaces of the fifth lens element includes at least one critical point in an off-axis region thereof.

Abstract: Methods and apparatus for performing secure ranging measurements between wireless devices are disclosed herein according to embodiments of the present invention. The described embodiments use key values to indicate which LTF sequence (e.g., LTF measurement exchange) to use for performing wireless ranging measurements. A LTF sequence that is received by a wireless device that does not correspond with the associated key value is determined to be invalid. Invalid LTF sequences may be disregarded as signal noise.

Abstract: A method for selecting a reference frame, an electronic device, and a storage medium. The method includes: calculating a sum of absolute values of pixel brightness differences of corresponding pixel locations in a current frame and a previous frame in a video; determining frame attribute of the current frame based on the sum of absolute values of pixel brightness differences, the frame attribute including a raw frame and a duplicate frame; counting a number of raw frames in M historical frames previous to the current frame; obtaining a current frame interpolation step size based on the number of raw frames in the M historical frames; obtaining a next frame phase to be interpolated based on a current frame interpolation phase and the current frame interpolation step size; and determining an interpolation reference frame based on the next frame to be interpolated.

Abstract: An integrated circuit provided here includes a N-bit flip-flop and a first clock cell. The N-bit flip-flop includes first cell of a first bit and a second cell of a second bit. An output signal from the first cell is inputted into the second cell in response to a first clock signal. The first and second cells have different widths and are arranged in a first row of multiple first cell rows and a first row of multiple second cell rows respectively. The first cell rows and the second cell rows have different row heights. The first clock cell outputs the first clock signal and is arranged in the first row of the second cell rows to abut the first cell.

Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Abstract: The present disclosure provides a microfluidic device, including a bottom substrate, an electrowetting-on-dielectric (EWOD) chip, a circuit board, a dielectric film, and a motor. The EWOD chip is disposed on the bottom substrate, and the circuit board is arranged on the EWOD chip. The circuit board includes a circuit area that is electrically connected to the EWOD chip, and the empty area is adjacent to the circuit area and the EWOD chip is exposed. The dielectric film is disposed on the empty area of the circuit board and covers the exposed EWOD chip. The motor is disposed under the bottom substrate, and one end of the motor has a magnetic structure, so that the magnetic structure can move closer to or away from the bottom substrate.

Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.