Abstract: A light-emitting device, includes: a substrate; a light-emitting structure formed on the substrate and including a first portion, and a second portion where no optoelectronic conversion occurs therein; and a first electrode located on both the first portion and the second portion.

Abstract: A wireless control device adapted to detect a signal from a signal source for generating a corresponding first sensing signal and wirelessly transmit the first sensing signal to a host is provided. The wireless control device includes a position calibrator and an accessory. The position calibrator includes a first main body, a first coupling structure disposed on the first main body, at least one position sensing element adapted to detect the signal, a first microprocessor electrically connected to the position sensing element and a wireless transmitting module electrically connected to the first microprocessor and wirelessly transmitting the first sensing signal to the host. The accessory includes a second main body and a second coupling structure disposed on the second main body. A position calibrator and an accessory detachably assembled with the position calibrator to form a wireless control device are also provided.

Abstract: A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening. A coating layer is coated over the photo resist, wherein the coating layer includes a first portion in the first opening, and a second portion over the photo resist. A top surface of the first portion is lower than a top surface of the second portion. The coating layer, the photo resist, and the implanted region are etched to form a second opening in the implanted region.

Abstract: A hybrid system includes a printed circuit board (PCB) having a main surface, a package-on-package (PoP) having a bottom package mounted on the main surface of the PCB and a top package stacked on the bottom package, and a multi-chip package (MCP) on the main surface of the PCB. The bottom package includes a system-on-chip (SoC) and the top package includes at least one on-package dynamic random access memory (DRAM) die accessible to the SoC. The MCP includes at least one on-board DRAM die accessible to the SoC via a PCB trace.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.

Abstract: This description relates to a method of forming the gate electrode of a semiconductor device, the method including providing a substrate comprising a dummy gate electrode (DGE), a source/drain (S/D) region, a spacer on a dummy gate sidewall, and an isolation feature, depositing a contact etch stop layer (CESL) over the DGE, the S/D region and the spacer, depositing an interlayer dielectric (ILD) layer over the CESL, performing a first chemical mechanical polishing (CMP) to expose the CESL over the DGE, performing a second CMP to expose the DGE, removing an upper portion of the CESL and the spacer, and performing a third CMP to expose the CESL over the S/D region to produce a structure in which an entire top surface of the CESL over the S/D region and isolation feature is substantially co-planar with a top surface of the DGE.

Abstract: A storage device carrier includes a first frame and a second frame. The first frame includes two opposite sidewalls. Two through holes are defined in each of the sidewalls, for allowing screws to extend therethrough. The second frame is detachably mounted in the first frame. The second frame includes two opposite side plates. Each side plate defines two through slots for allowing screws and unthreaded fasteners to extend therethrough. When the second frame is mounted in the first frame, the side plates of the second frame respectively abut against the sidewalls of the first frame, and the through slots of the side plates respectively align with the through holes of the sidewalls. A mounting apparatus having the storage device is also provided.

Abstract: A carrier includes a frame defining a first space configured to accommodate a first type of hard disk drive, and an adjusting mechanism rotatably coupled to the frame. The adjusting mechanism is transitionable between: (i) a first configuration in which the adjusting mechanism is located outside the first space defined by the frame, and (ii) a second configuration in which the adjusting mechanism is located inside the first space, the adjusting mechanism and the frame cooperatively define a second space configured to accommodate a second type of hard disk drive different from the first type of hard disk drive.

Abstract: A method for preparing a wafer includes forming a film layer on a substrate of the wafer; coating the film layer with a photoresist layer; exposing a first portion of the photoresist layer to a beam of light; and patterning a second portion of the photoresist layer after performing exposing the first portion of the photoresist layer. A cross-link reaction is caused on the first portion of the photoresist layer and the first portion of the photoresist layer is converted to a reacted first portion of the photoresist layer. The reacted first portion of the photoresist layer is near an edge of the wafer. The second portion of the photoresist layer is different from the reacted first portion of the photoresist layer. The second portion of the photoresist layer is converted to a patterned second portion of the photoresist layer.

Abstract: A display is disclosed. The display includes a display panel including pixel units in an image-displaying region. Each of the pixel units includes an AND gate and a pixel electrode electrically connected to an output terminal of the AND gate.

Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins coupled to a plurality of conductive traces of a printed circuit board (PCB), and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The driving units are divided into a plurality of first driving units and second driving units. According to the control signals, the first driving units provide the data to a memory device of the PCB via the corresponding pins and the corresponding conductive traces of PCB, and the second driving units provide a constant voltage to the corresponding conductive traces of PCB via the corresponding pins. The conductive traces corresponding to the second driving units are separated by the conductive traces corresponding to the first driving units on the PCB.

Abstract: A storage device carrier includes a first frame and a second frame. The first frame includes two opposite sidewalls. Two through holes are defined in each of the sidewalls, for allowing screws to extend therethrough. The second frame is detachably mounted in the first frame. The second frame includes two opposite side plates. Each side plate defines two through slots for allowing screws and unthreaded fasteners to extend therethrough. When the second frame is mounted in the first frame, the side plates of the second frame respectively abut against the sidewalls of the first frame, and the through slots of the side plates respectively align with the through holes of the sidewalls. A mounting apparatus having the storage device is also provided.

Abstract: A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.

Abstract: A cover opening structure including a case, a cover, a pushing button, a pushing unit and an axle is provided. The cover has a first portion having a first side, a second portion having a second side connected to the case, and a connecting portion connected therebetween, wherein the connecting portion is softer than the first and second portions. The pushing button disposed on the case has a body and an inserting portion extended from the body. The pushing unit has a first end, a second end and a leaning portion connected therebetween and is inserted between the body and the first end. The axle is disposed at the case while the leaning portion leans against the axle. The pushing unit rotates about the axle while the first end moves downward and the second end moves upward to push up the first portion when the pushing button is moved.

Abstract: A carrier includes a frame defining a first space configured to accommodate a first type of hard disk drive, and an adjusting mechanism rotatably coupled to the frame. The adjusting mechanism is transitionable between: (i) a first configuration in which the adjusting mechanism is located outside the first space defined by the frame, and (ii) a second configuration in which the adjusting mechanism is located inside the first space, the adjusting mechanism and the frame cooperatively define a second space configured to accommodate a second type of hard disk drive different from the first type of hard disk drive.

Abstract: A ceramic capacitor dielectric material includes BaTiO3, BaZrO3, SrTiO3, MgCO3, SiO2, and at least one compound selected from transition element and rare earth element. The amount of the BaTiO3 in the ceramic capacitor dielectric material is 40-80 mol %; the amount of the BaZrO3 is 20-40 mol %; and the amount of the SrTiO3 is smaller than or equal to 20 mol %. The permittivity of the ceramic capacitor dielectric material is larger than 350, and the dielectric loss is lower than 0.5%. Moreover, the resistivity can reach 1012 ?-cm under room temperature, and further reach 1011 ?-cm at 125° C. Besides, the performance of the capacitance change rate of the ceramic capacitor dielectric material under DC bias is excellent, thus the ceramic capacitor dielectric material can fulfil the X7T dielectric properties of EIA.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a printed circuit board (PCB) with a first signal path and a second signal path therein, a first finger disposed on the first signal path, a second finger disposed on the second signal path, a controller disposed on the PCB and coupled to a first memory via the first finger and to a second memory via the second finger, and a damping device disposed on the second signal path. The first and second signal paths share a common segment between the controller and a branch point on the PCB. The damping device is disposed between the second finger and the branch point. The distance between the first finger and the branch point within the first signal path is smaller than the distance between the second finger and the branch point within the second signal path.