Abstract: Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated.

Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Abstract: To protect device keys, an optical media recording device capable of performing AACS encryption on data does not have any device keys, and the optical media recording device performs AACS encryption by activating recording software stored in a memory the optical media recording device, and utilizing a pre-calculated media key stored in the memory of the optical media recording device to perform AACS encryption on the data.

Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

Abstract: A color filter provided in the invention includes a substrate, a first color filter pattern and a second color filter pattern. The substrate has at least one first pixel region and at least one second pixel region adjacent to the first pixel region. The first color filter pattern is disposed on the substrate and includes a first central pattern and first protruding patterns connected to the first central pattern and protruding outwardly from the first central pattern so that a portion of the first protruding patterns are located in the second pixel region. The second color filter pattern includes a second central pattern located within the second pixel region.

Abstract: A soft error protection device is disclosed, which comprises a soft error resilient latch (SERL) and a latch coupled to a detection device and receiving a soft error pulse and a clock (CLK) signal respectively outputted by an electronic element and a CLK generator. The SERL delays the soft error pulse. In the period of a negative level of the CLK signal, the SERL stores the delayed soft error pulse corresponding to the negative level and used as a first detection data. Meanwhile, the latch stores the soft error pulse as a second detection data. The detection device receives the CLK signal, the first and second detection datum, and compares the first and second detection datum to send out a detection signal when the CLK signal rises from the negative level to a positive level.

Abstract: This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

Abstract: A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.

Abstract: A light-emitting device, includes: a substrate; a light-emitting structure formed on the substrate and including a first portion, and a second portion where no optoelectronic conversion occurs therein; and a first electrode located on both the first portion and the second portion.

Abstract: A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.

Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

Abstract: This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.

Abstract: A power supply method for an universal serial bus apparatus is provided. The USB apparatus includes an upstream port module and a plurality of downstream port modules. The power supply method comprises the following steps: setting a maximum charging port number for the downstream port modules according to the connection configuration between the upstream port module and a host, and the condition of power supply from an external power supply; detecting the coupling condition of the electronic apparatuses to the downstream port modules so as to customize a specific charging specification for one of the electronic apparatuses; respectively providing a plurality of power to the electronic apparatuses according to the specific charging specification and the maximum charging port number. Thus, the electronic apparatuses enable to be charged with maximum charging currents and operate normally under the USB specification without being affected.

Abstract: A mounting apparatus for an expansion card includes a shaft fixed to the expansion card, and a rotary member rotatably mounted to the shaft. The rotary member includes a cam, an operation portion opposite to the cam, and a latching portion formed between the cam and the operation portion. When fitting the expansion card to an expansion socket, the operation portion is operated to rotate the rotary member about the shaft, and the latching portion is latched to the expansion socket. When disassembling the expansion card from the expansion socket, the cam is levered against a top of the expansion socket to lift out the expansion card, thereby disassembling the expansion card from the expansion socket.

Abstract: A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

Abstract: A hinge mechanism suitable for a foldable electronic device has a first body, a second body and a hinging-body. The hinge mechanism includes a first cradle, a second cradle, a pair of pivoting-shafts, a pair of position-limiting elements, a set of gears and a positioning element. The positioning-element is fixed to the hinging-body and structurally independent from the position-limiting elements, pivoted to the pivoting-shafts so as to be detachably assembled with the position-limiting elements. The first body rotates relatively to the hinging-body through the first cradle rotates the pivoting-shaft fixed to the first cradle relatively to the positioning element so as to rotate the set of gears, make the second cradle rotate the pivoting-shaft fixed to the second cradle relatively to the positioning-element and bring the second body for rotation relatively to the hinging-body. Additionally, a foldable electronic device is also provided.

Abstract: A package on package (PoP) structure is disclosed. The PoP structure includes a top package and a bottom package disposed thereunder. The top package includes a first substrate and a first die mounted onto the first substrate. The first substrate has a thermal conductivity which is more than 70 W/(m×K). The bottom package includes a second substrate and a second die mounted onto the second substrate. An upper surface of the second die is in thermal contact with a lower surface of the first substrate.

Abstract: The present invention provides an imaging and measuring apparatus for the surface and the internal interface of an object, which comprises a broadband wave source, a wave-splitting structure, a wave-delaying device, a reflecting component, and a sensor. The broadband wave source transmits a broadband incident wave. The wave-splitting structure splits the broadband incident wave into a first incident beam, a second incident beam, and a third incident beam. The first incident beam is illuminated on an object under test, which reflects a measuring beam. The wave-delaying device receives the second incident beam and reflects a reference beam. The reflecting component receives the third incident beam and reflects a calibration beam. The sensor receives a first interference signal of the measuring beam and the reference beam, and a second interference signal of the reference beam and the calibration beam.

Abstract: An electronic device including a main body, a rotating base, a motherboard and a driving module is provided. The rotating base has a first vent. The rotating base is pivoted to the main body and suitable for being rotated between an operating position and a retracting position. When the rotating base is located at the operating position, the first vent is exposed from the main body, and when the rotating base is located at the retracting position, the first vent is retracted in the main body. The driving module includes a controlling element and a first locking element. The controlling element is disposed on the main body and suitable for moving between an enable position and a disable position. The first locking element is connected to the controlling element, and the controlling element drives the first locking element to position the rotating base.