Abstract: A ceramic capacitor dielectric material includes BaTiO3, BaZrO3, SrTiO3, MgCO3, SiO2, and at least one compound selected from transition element and rare earth element. The amount of the BaTiO3 in the ceramic capacitor dielectric material is 40-80 mol %; the amount of the BaZrO3 is 20-40 mol %; and the amount of the SrTiO3 is smaller than or equal to 20 mol %. The permittivity of the ceramic capacitor dielectric material is larger than 350, and the dielectric loss is lower than 0.5%. Moreover, the resistivity can reach 1012 ?-cm under room temperature, and further reach 1011 ?-cm at 125° C. Besides, the performance of the capacitance change rate of the ceramic capacitor dielectric material under DC bias is excellent, thus the ceramic capacitor dielectric material can fulfil the X7T dielectric properties of EIA.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a printed circuit board (PCB) with a first signal path and a second signal path therein, a first finger disposed on the first signal path, a second finger disposed on the second signal path, a controller disposed on the PCB and coupled to a first memory via the first finger and to a second memory via the second finger, and a damping device disposed on the second signal path. The first and second signal paths share a common segment between the controller and a branch point on the PCB. The damping device is disposed between the second finger and the branch point. The distance between the first finger and the branch point within the first signal path is smaller than the distance between the second finger and the branch point within the second signal path.

Abstract: A display apparatus includes a light permeable substrate, dummy pixels, a peripheral wiring layer and a display element layer. The dummy pixels are disposed on the light permeable substrate. Each of the dummy pixels includes a dummy pattern controlling layer. The peripheral wiring layer is disposed on the light permeable substrate for applying voltages having the same polarity to the dummy pattern controlling layers. The display element layer covers the light permeable substrate and the dummy pixels. The peripheral wiring layer and the dummy pattern controlling layer are spaced apart by a gap. The gap allows light to be reflected from the display element layer to the light permeable substrate.

Abstract: A connector is provided, including a housing, a conductive contact disposed in the housing, a hollow structure disposed in the housing, and an electrical connecting mechanism. The electrical connecting mechanism is movably disposed in the hollow structure, including a first conductive member, a first spring, a second conductive member, and a second spring. The first spring connects the first conductive member with the hollow structure and provides a first spring force such that the first conductive member protrudes from the hollow structure. The second conductive member and the second spring are movably disposed in the first conductive member, wherein the second spring connects to the first and second conductive members and provides a second spring force such that the second conductive member protrudes from the first conductive member. Specifically, the second conductive member and the conductive contact are spaced apart by a distance.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins, and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The pins are coupled to a device via a plurality of conductive traces of a printed circuit board (PCB). The control signals control each of the driving units to selectively provide the data or one specific shielding pattern via the corresponding pin and the corresponding conductive trace of PCB to the device.

Abstract: A chip package includes a first die encapsulated by a molding compound; a board comprising a chip mounting surface; a redistributed layer (RDL) structure on an active surface of the first die and between the die and the chip mounting surface; and a discrete passive device embedded in the molding compound and situated in close proximity to a side edge of the first die.

Abstract: A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening. A coating layer is coated over the photo resist, wherein the coating layer includes a first portion in the first opening, and a second portion over the photo resist. A top surface of the first portion is lower than a top surface of the second portion. The coating layer, the photo resist, and the implanted region are etched to form a second opening in the implanted region.

Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Abstract: A color filter includes a substrate, a first color filter pattern and a second color filter pattern. The substrate has at least one first pixel region and at least one second pixel region adjacent to the first pixel region. The first color filter pattern is disposed on the substrate and includes a first central pattern and first protruding patterns connected to the first central pattern and protruding outwardly from the first central pattern so that a portion of the first protruding patterns are located in the second pixel region. The second color filter pattern includes a second central pattern located within the second pixel region.

Abstract: A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer.

Abstract: Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated.

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.

Abstract: A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.

Abstract: A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group.

Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Abstract: A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening. A coating layer is coated over the photo resist, wherein the coating layer includes a first portion in the first opening, and a second portion over the photo resist. A top surface of the first portion is lower than a top surface of the second portion. The coating layer, the photo resist, and the implanted region are etched to form a second opening in the implanted region.

Abstract: A display is disclosed. The display includes a display panel including pixel units in an image-displaying region. Each of the pixel units includes an AND gate and a pixel electrode electrically connected to an output terminal of the AND gate.

Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.