Abstract: A photovoltaic inverter includes a casing, at least one circuit board located in the casing, a current sensor located on the at least one circuit board, an arc detector located on the at least one circuit board, a self-test coil located on the at least one circuit board, and at least one direct current input terminal located on the casing and connected to the at least one circuit board, wherein the self-test coil is configured to deliver a test signal to be sensed by the arc detector, and the direct current input terminal is configured to deliver a direct current through the arc detector, wherein the current sensor is configured to detect a magnitude of the direct current passing through the direct current input terminal.

Abstract: An ambient light sensor includes a substrate, a metasurface disposed on the substrate, and an aperture layer disposed on the substrate. The metasurface includes a plurality of nanostructures and a filling layer laterally surrounding the plurality of nanostructures. The aperture layer laterally separates the metasurface into a plurality of sub-meta groups.

Abstract: Methods and apparatuses for handling device-to-device feedback transmission in a wireless communication system are disclosed herein. In one method, a first device receives a configuration for operating in a network scheduling mode for acquiring sidelink resources. The first device receives a sidelink control information with a report request from a second device. The first device triggers or is triggered to transmit a report to the second device in response to the report request. If the first device has no available sidelink resource for transmitting the report, the first device triggers a scheduling request. The first device transmits a signaling of the scheduling request to the network. The first device receives a sidelink grant from the network. The first device utilizes sidelink resource(s) indicated by the sidelink grant to transmit the report to the second device.

Abstract: A semiconductor device includes a first buried layer and a second buried layer both have a first conductivity type and are disposed in a substrate, where the second buried layer is disposed on the first buried layer. A first well region has the first conductivity type and is disposed above the second buried layer. A second well region has a second conductivity type and is adjacent to the first well region. A deep trench isolation structure is disposed in the substrate and surrounds the first and second well regions, where the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer. A source region is disposed in the second well region. A drain region is disposed in the first well region. A gate electrode is disposed on the first and second well regions.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

Abstract: In an example, a device, with a configuration of a sidelink resource pool comprising sidelink reference signal resources, determines candidate frequency resources of sidelink control channel in a slot in the sidelink resource pool. The candidate frequency resources are determined based on one or more parameters, one or more indexes and/or one or more identities associated with a plurality of candidate sidelink reference signal resources in the slot. The device performs monitoring on the candidate frequency resources. The device receives a sidelink control information (SCI) using a first frequency resource of the sidelink control channel. The candidate frequency resources include the first frequency resource of the sidelink control channel. The device measures a sidelink reference signal on a first sidelink reference signal resource in the slot.

Abstract: The present invention relates to a new electronic component package and its manufacturing method, especially the package of an optoelectronic component. The package comprises an electronically conductive base, an electronically conductive cap, and at least one electronic component. The base has an upper surface, a lower surface, and at least one through hole sealed with a conducting feedthrough surrounded by a ring of insulating material. The electronic component is fixed on the upper surface of the base and is electrically connected to the conducting feedthroughs and/or the base. The base and the cap are sealed by welding.

Abstract: A method and apparatus are disclosed. In an example from the perspective of a device with a configuration of a first sidelink resource pool including sidelink reference signal resources, the device determines a first sidelink reference signal resource in a slot in the first sidelink resource pool. The device determines a frequency resource of a sidelink control channel associated with the first sidelink reference signal resource based on one or more parameters of the first sidelink reference signal resource, an index of the first sidelink reference signal resource, and/or an identity of the first sidelink reference signal resource. The device transmits, using the frequency resource of the sidelink control channel and in the slot in the first sidelink resource pool, a sidelink control information (SCI). The device transmits a sidelink reference signal on the first sidelink reference signal resource in the slot in the first sidelink resource pool.

Abstract: A nerve stimulation system includes an electrode, an electrode controlling device coupled to the electrode and configured to control the electrode to electrically stimulate a peripheral nerve according to a nerve stimulation signal, and a signal generating device coupled to the electrode controlling device and configured to generate the nerve stimulation signal. The nerve stimulation signal is a signal with a square envelope. The square envelope periodically includes an on-time period with a pulse amplitude and an off-time period without the pulse amplitude, and a ratio of the on-time period and the off-time period is not less than 1, and a length of the off-time period is not longer than 5 seconds.

Abstract: Provided herein, inter alia, are compositions including engineered NK cells and methods for preparing the same. The engineered NK cells provided herein include integrated nucleic acid sequences encoding Cas9 proteins (e.g. dCas9). The engineered NK cells are contemplated to be effective for treating and/or preventing cancer, particularly leukemia.

Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE receives one or more signals indicative of a first Physical Uplink Shared Channel (PUSCH) and a second PUSCH on a first cell and in a Transmission Time Interval (TTI). The UE determines to transmit a first Uplink Control Information (UCI) in the TTI, wherein the first UCI overlaps with the first PUSCH and the second PUSCH in time domain. The UE selects the first PUSCH for multiplexing the first UCI based on whether the UE is configured with joint Hybrid Automatic Repeat Request (HARQ) feedback mode or separate HARQ feedback mode. The UE transmits the first PUSCH and the second PUSCH on the first cell, wherein the first PUSCH transmitted on the first cell includes the first UCI.

Abstract: A semiconductor package may include a package substrate including a dummy via on a first side of the package substrate, an interposer module on a second side of the package substrate opposite the first side of the package substrate, and a stiffener ring on the second side of the package substrate and including an edge that is substantially aligned with the dummy via.

Abstract: An immersion cooling system includes a cooling tank, an immersion unit, a first disturbing element, and a first maintaining element. The cooling tank has a receiving portion. The immersion unit is in the receiving portion, and the immersion unit includes a boiler plate. The first disturbing element has a first convex surface. The first maintaining element maintains the first disturbing element to allow a convex direction of the first convex surface towards the boiler plate, and a first predetermined distance is between the first convex surface and the boiler plate.

Abstract: An immersion cooling system including a cooling tank, an immersion unit, and a baffle assembly is provided. The cooling tank has a receiving portion. The immersion unit is in the receiving portion and includes a boiler plate. The baffle assembly divides the receiving portion into an inner upper portion, an inner lower portion, and a peripheral portion. The boiler plate is in the inner lower portion, and a width of the inner upper portion is less than or equal to a width of the boiler plate.

Abstract: An immersion cooling system including a cooling tank, an immersion unit, a plurality of piezoelectric units, and a piezoelectric driver is provided. The cooling tank has a receiving portion. The immersion unit is in the receiving portion and the immersion unit includes a boiler plate. One or more channels are between the piezoelectric units, and the at least one channel is in communication with the boiler plate. The piezoelectric driver is for driving each of the piezoelectric units to generate a deformation.

Abstract: An image sensor includes a substrate having first and second surfaces opposite to each other, an image pixel area, and a black level calibration (BLC) area adjacent to the image pixel area. The BLC area includes a dark current sensing circuit including photo diodes disposed in the substrate, a first seal ring disposed over the second surface and surrounding the image pixel area in plan view, a second seal ring disposed over the second surface and surrounding the image pixel area in plan view such that the dark current sensing circuit is disposed between the first and second seal rings, an opaque cover disposed over the first surface and covering the dark current sensing circuit, the first and second seal rings, and one or more first trench isolation structures extending from the first surface to an inside the substrate and disposed between the first seal ring and the opaque cover.

Abstract: A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE receives one or more signals indicative of a first Physical Uplink Shared Channel (PUSCH) and a second PUSCH on a first cell and in a Transmission Time Interval (TTI). The UE determines to transmit a first Uplink Control Information (UCI) in the TTI, wherein the first UCI overlaps with the first PUSCH and the second PUSCH in time domain. The UE selects the first PUSCH for multiplexing the first UCI based on whether the UE is configured with joint Hybrid Automatic Repeat Request (HARQ) feedback mode or separate HARQ feedback mode. The UE transmits the first PUSCH and the second PUSCH on the first cell, wherein the first PUSCH transmitted on the first cell includes the first UCI.

Abstract: A method and apparatus are disclosed from the perspective of a User Equipment (UE) in a wireless communication system. The method can include receiving a configuration for a first set of power control information and a second set of power control information, receiving a Downlink Control Information (DCI) scheduling one or more Physical Uplink Shared Channels (PUSCHs), wherein the DCI comprises a first Sounding Reference Signal Resource Indicator (SRI) field and a second SRI field, determining a first Identifier (ID) directly based on value indicated by the first SRI field, wherein the first ID is a power control information ID in the first set of power control information, determining a second ID based on a value indicated by the second SRI field and the number of layers, and transmitting the one or more PUSCHs based on transmit power derived from the power control information of the first ID or the power control information of the second ID.

Abstract: Provided is a clock switching device including a first latch circuit, a second latch circuit, and a switching circuit. The first latch circuit latches a first selection signal based on triggering of a first clock signal. The second latch circuit latches a second selection signal based on triggering of a second clock signal. A reset terminal of the second latch circuit is coupled to the first latch circuit. The second latch circuit is selectively reset based on an output of the first latch circuit. The switching circuit is coupled to an output terminal of the first latch circuit and an output terminal of the second latch circuit. The switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the selection signals.