Abstract: A device includes a semiconductor fin protruding from a substrate, a first gate stack over the semiconductor fin and a second gate stack over the semiconductor fin, a first source/drain region in the semiconductor fin adjacent the first gate stack and a second source/drain region in the semiconductor fin adjacent the second gate stack, a first layer of a first dielectric material on the first gate stack and a second layer of the first dielectric material on the second gate stack, a first source/drain contact on the first source/drain region and adjacent the first gate stack, a first layer of a second dielectric material on a top surface of the first source/drain contact, and a second source/drain contact on the second source/drain region and adjacent the second gate stack, wherein the top surface of the second source/drain contact is free of the second dielectric material.

Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

Abstract: Various embodiments of the present disclosure are directed towards a microphone including a particle filter disposed between a microelectromechanical systems (MEMS) substrate and a carrier substrate. A MEMS device structure overlies the MEMS substrate. The MEMS device structure includes a diaphragm having opposing sidewalls that define a diaphragm opening. The carrier substrate underlies the MEMS substrate. The carrier substrate has opposing sidewalls that define a carrier substrate opening underlying the diaphragm opening. A filter stack is sandwiched between the carrier substrate and the MEMS substrate. The filter stack includes an upper dielectric layer, a lower dielectric layer, and a particle filter layer disposed between the upper and lower dielectric layers. The particle filter layer includes the particle filter spaced laterally between the opposing sidewalls of the carrier substrate.

Abstract: Various embodiments of the present disclosure are directed towards a microphone including a support structure layer disposed between a particle filter and a microelectromechanical systems (MEMS) structure. A carrier substrate is disposed below the particle filter and has opposing sidewalls that define a carrier substrate opening. The MEMS structure overlies the carrier substrate and includes a diaphragm having opposing sidewalls that define a diaphragm opening overlying the carrier substrate opening. The particle filter is disposed between the carrier substrate and the MEMS structure. A plurality of filter openings extend through the particle filter. The support structure layer includes a support structure having one or more segments spaced laterally between the opposing sidewalls of the carrier substrate. The one or more segments of the support structure are spaced laterally between the plurality of filter openings.

Abstract: An intelligence-defined optical tunnel network system includes multiple Optical Switch Interconnect Sub-systems (OSIS), in which a first OSIS is configured to transmit a first lateral transmission optical signal via a first line to a second OSIS, and transmit a second lateral transmission optical signal via a second line to the second OSIS. The second OSIS includes a failover sub-module and a micro-control unit. The failover sub-module is configured to output one of the first and the second lateral transmission optical signal based on a selective signal. The micro-control unit is configured to output the selective signal to the failover sub-module to control the failover sub-module output the second lateral transmission optical signal if a signal intensity of the first lateral transmission optical signal is lower than a threshold value.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.

Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.

Abstract: A headband adjustment structure includes a rotary adjusting assembly, a wearing unit having an adjustable accommodation space, a cable management module located between the wearing unit and the rotary adjusting assembly for carrying a cable, an adjustment gear set linkably coupled to the cable management module, and a driving rotation shaft set passing through the wearing unit and the cable management module, and linkably coupled to the wearing unit and the adjustment gear set, and coaxially connected to the rotary adjusting assembly. When the rotary adjusting assembly rotates the driving rotation shaft set, the driving rotation shaft set synchronously moves the wearing unit to adjust the adjustable accommodation space, and moves the cable management module through the adjustment gear set. The amount of the movement of the cable management module is different from that of the wearing unit.

Abstract: A MEMS device includes a first layer and a second layer including a same material, a third layer disposed between the first layer and the second layer, a first air gap separating the first layer and the third layer, a second air gap separating the second layer and the third layer, a plurality of first pillars exposed to the first air gap and arranged in contact with the first layer and the third layer, a plurality of second pillars exposed to the second air gap and arranged in contact with the second layer and the third layer.

Abstract: In some embodiments, a wireless local area network (WLAN) front-end can be implemented on a semiconductor die having a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to support the transmit and receive operations.

Abstract: A device includes a first biosensor of a biosensor array; a second biosensor of a biosensor array; a readout circuit electrically connected to the biosensor array; a decoder electrically connected to the biosensor array; a voltage generator electrically connected to the biosensor array; and a decision system electrically connected to the voltage generator and the readout circuit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. The semiconductor device structure also includes an insulating structure that includes a first insulating layer formed between and separating from the first fin and the second fin, a second insulating layer embedded in the first insulating layer, a first capping layer formed in the first insulating layer to cover a top surface of the second insulating layer, and a second capping layer in the first capping layer.

Abstract: The present disclosure relates to a method of forming an integrated chip structure. The method includes forming a plurality of interconnect layers within a dielectric structure over a substrate. A dielectric layer arranged along a top of the dielectric structure is patterned to define a via hole exposing an uppermost one of the plurality of interconnect layers. An extension via is formed within the via hole and one or more conductive materials are formed over the dielectric layer and the extension via. The one or more conductive materials are patterned to define a sensing electrode over and electrically coupled to the extension via. A microelectromechanical systems (MEMS) substrate is bonded to the substrate. The MEMs substrate is vertically separated from the sensing electrode.

Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Abstract: An electronic device including a first body, a supporting member, a second body, and an input assembly is provided. The first body is provided with a front end and a rear end opposite to each other. One terminal end of the supporting member is pivotally connected to the rear end of the first body. The second body is pivotally connected to the other terminal end of the supporting member. The input assembly is rotatably connected to the second body and is suitable for being carried by the first body. When a lower edge of the second body is located at the front end of the first body, the input assembly protrudes out from the front end of the first body.

Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.

Abstract: An integrated circuit (IC) with an integrated microelectromechanical systems (MEMS) structure is provided. In some embodiments, the IC comprises a semiconductor substrate, a back-end-of-line (BEOL) interconnect structure, the integrated MEMS structure, and a cavity. The BEOL interconnect structure is over the semiconductor substrate, and comprises wiring layers stacked in a dielectric region. Further, an upper surface of the BEOL interconnect structure is planar or substantially planar. The integrated MEMS structure overlies and directly contacts the upper surface of the BEOL interconnect structure, and comprises an electrode layer. The cavity is under the upper surface of the BEOL interconnect structure, between the MEMS structure and the BEOL interconnect structure.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.

Abstract: An embodiment is a MEMS device including a first MEMS die having a first cavity at a first pressure, a second MEMS die having a second cavity at a second pressure, the second pressure being different from the first pressure, and a molding material surrounding the first MEMS die and the second MEMS die, the molding material having a first surface over the first and the second MEMS dies. The device further includes a first set of electrical connectors in the molding material, each of the first set of electrical connectors coupling at least one of the first and the second MEMS dies to the first surface of the molding material, and a second set of electrical connectors over the first surface of the molding material, each of the second set of electrical connectors being coupled to at least one of the first set of electrical connectors.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.