Patents by Inventor Chun Yan

Chun Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240124350
    Abstract: A quantum dot composite structure and a method for forming the same are provided. The quantum dot composite structure includes: a glass particle including a glass matrix and a plurality of quantum dots located in the glass matrix, wherein at least one of the plurality of quantum dots includes an exposed surface in the glass matrix; and an inorganic protective layer disposed on the glass particle and covering the exposed surface.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 18, 2024
    Inventors: Ching LIU, Wen-Tse HUANG, Ru-Shi LIU, Pei Cong YAN, Chai-Chun HSIEH, Hung-Chun TONG, Yu-Chun LEE, Tzong-Liang TSAI
  • Publication number: 20240113575
    Abstract: A hybrid permanent magnet motor rotor rotates around a central axis, and includes: a rotor core provided with a plurality of magnet installation slots; and a plurality of magnet parts embedded inside a plurality of magnet installation slots respectively, wherein the rotor is provided with a plurality of first magnetic pole parts and a plurality of second magnetic pole parts, the magnetic poles of the first magnetic pole part and the second magnetic pole part are arranged in opposite and alternately in the circumferential direction, and the magnetic placement of the first magnetic pole part is different from that of the second magnetic pole part, the amount of magnets used in the second magnetic pole part is greater than that used in the first magnetic pole part.
    Type: Application
    Filed: August 25, 2023
    Publication date: April 4, 2024
    Inventors: Kuan YANG, Pei-Chun SHIH, Ta-Yin LUO, Guo-Jhih YAN, Sheng-Chan YEN, Cheng-Tsung LIU
  • Publication number: 20240088293
    Abstract: An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.
    Type: Application
    Filed: October 5, 2022
    Publication date: March 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ya Chiu, Ssu-I Fu, Chin-Hung Chen, Jin-Yan Chiou, Wei-Chuan Tsai, Yu-Hsiang Lin
  • Publication number: 20240084012
    Abstract: An isolated bispecific antibody or antigen-binding portion thereof includes a first chain which specifically binds to human PD-1(hPD-1) and blocks the interaction between hPD-1 and PD-L1, and a second chain which specifically binds to human CD47 and inhibits its interaction with SIRP-alpha, where the first chain and the second chain are coupled in a knob-in-hole format through their respective CH3 domain.
    Type: Application
    Filed: December 31, 2021
    Publication date: March 14, 2024
    Inventors: Chun-Jen LIN, Cheng-Chi CHAO, Chang-Hsin Chen, Gloria Guohong ZHANG, Guochen YAN
  • Publication number: 20230386799
    Abstract: A focus ring for a plasma-based semiconductor processing tool is designed to provide and/or ensure etch rate uniformity across a wafer during a plasma etch process. The focus ring may include an angled inner wall that is angled away from a center of the focus ring to direct a plasma toward the wafer. The angle of the angled inner wall may be greater than approximately 130 degrees relative to the top surface of the wafer and/or may be less than approximately 50 degrees relative to an adjacent lower surface of the focus ring to reduce and/or eliminate areas of overlapping plasma on the wafer (which would otherwise cause non-uniform etch rates). Moreover, an inner diameter may be configured to be in a range of approximately 209 millimeters to 214 millimeters to further reduce and/or eliminate areas of overlapping plasma on the wafer.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Sheng-Chieh HUANG, Chang Kuang TSO, Chou Feng LEE, Chung-Hsiu CHENG, Jr-Sheng CHEN, Chun Yan CHEN, Chih-Hsien HSU, Chin-Tai HUNG
  • Publication number: 20230337694
    Abstract: The invention provides a fat composition comprising from 20% to 50% by weight of palmitic acid (C16:0), from 20% to 45% by weight of oleic acid (C18:1), and from 17% to 40% by weight of linoleic acid (C18:2), said percentages of acid being based on the total weight of C8 to C24 fatty acids; wherein the fat composition has a weight ratio of oleic acid (C18:1) to linoleic acid (C18:2) of from 0.4 to 2.4; wherein the percentage of palmitic acid on the second position of triglyceride (SN-2 of C16:0) is at least 40% based on the total amount of palmitic acid; and wherein the fat composition comprises at most 5.0% by weight of PPP triglycerides and has a weight ratio of OPL triglycerides to OPO triglycerides from 0.80 to 1.60 based on the total glycerides present in the fat composition, wherein O is oleic acid, P is palmitic acid and L is linoleic acid.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 26, 2023
    Inventors: Kim Leong CHUA, You Chun YAN, Jun MA, Sze Hui NG, Suharulpazillah CHE NORDIN
  • Patent number: 11769652
    Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jr-Sheng Chen, An-Chi Li, Shih-Che Huang, Chih-Hsien Hsu, Zhi-Hao Huang, Ming Chih Wang, Yu-Pei Chiang, Chun Yan Chen
  • Publication number: 20230205441
    Abstract: Disclosed are a method for managing data and a storage device thereof. The storage device includes at least one memory including a plurality of planes, each plane includes a plurality of blocks, and peer blocks in different planes are belonged to operate in a multi-plane mode. The plurality of blocks are detected to find a unavailable block. Then, available blocks corresponding to the unavailable block in planes other than the plane where the unavailable block is located are marked as backup blocks that do not operate in the multi-plane mode. A first block with effective data is selected from the plurality of blocks operating in the multi-plane mode. Data of the first block is moved to a backup block in the same plane.
    Type: Application
    Filed: October 7, 2022
    Publication date: June 29, 2023
    Inventors: HUI WANG, CHUN YAN TANG, LIN SU
  • Patent number: 11649559
    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: May 16, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Bao, Chun Yan, Hua Chung, Schubert S. Chu
  • Patent number: 11651977
    Abstract: Methods for processing a workpiece are provided. Conducting a thermal treatment on a workpiece are provided. The workpiece contains at least one layer of metal. The method can include generating one or more species from a process gas. The process gas can include hydrogen or deuterium. The method can include filtering the one or more species to create a filtered mixture and exposing the workpiece to the filtered mixture. An oxidation process on a workpiece are provided. The method can be conducted at a process temperature of less than 350° C.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 16, 2023
    Assignees: BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY CO., LTD, MATTSON TECHNOLOGY, INC.
    Inventors: Shanyu Wang, Chun Yan
  • Patent number: 11647645
    Abstract: A cover plate used in an electronic device includes a glass layer and at least one transparent covering layer. The glass layer has a first surface and a second surface. The transparent covering layer contacts and is disposed on at least one of the first surface and the second surface, and the transparent covering layer is laminated with the glass layer. The cover plate has a Young's modulus of about 10 GPa to about 200 GPa.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: May 9, 2023
    Assignee: TPK Advanced Solutions Inc.
    Inventors: Chun Yan Wu, Lien-Hsin Lee, Shi Yuan Lian, Xian Bin Xu, Ming Qiang Fu, Ming Hsien Ko
  • Patent number: 11632609
    Abstract: A thin double-sided vibrating speaker includes a magnet member, a first vibration assembly and a second vibration assembly; the magnet member includes a main magnetic plate, a first magnetic path unit, a second magnetic path unit and side magnetic path units, the first magnetic path unit is disposed on one surface of the main magnetic plate, the second magnetic path unit is disposed on another surface of the main magnetic plate, the side magnetic path units are disposed on the main magnetic plate and correspond to two sides of the first magnetic path unit, the first vibration assembly is disposed on one surface of the magnet member, and the second vibration assembly is disposed on another surface of the magnet member. Accordingly, in addition to achieving the requirement of thinning, the thin double-sided vibrating speaker of the present disclosure also has the effect of vibration reduction and two-way sounding.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 18, 2023
    Assignee: FORTUNE GRAND TECHNOLOGY INC.
    Inventors: Ping-Yu Lee, Jian Lv, Yi-Yong Li, Zan-Hua Liu, Chun-Yan Zhang
  • Patent number: 11615946
    Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jr-Sheng Chen, An-Chi Li, Shih-Che Huang, Chih-Hsien Hsu, Zhi-Hao Huang, Alex Wang, Yu-Pei Chiang, Chun Yan Chen
  • Publication number: 20230066418
    Abstract: A focus ring for a plasma-based semiconductor processing tool is designed to provide and/or ensure etch rate uniformity across a wafer during a plasma etch process. The focus ring may include an angled inner wall that is angled away from a center of the focus ring to direct a plasma toward the wafer. The angle of the angled inner wall may be greater than approximately 130 degrees relative to the top surface of the wafer and/or may be less than approximately 50 degrees relative to an adjacent lower surface of the focus ring to reduce and/or eliminate areas of overlapping plasma on the wafer (which would otherwise cause non-uniform etch rates). Moreover, an inner diameter may be configured to be in a range of approximately 209 millimeters to 214 millimeters to further reduce and/or eliminate areas of overlapping plasma on the wafer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Sheng Chieh HUANG, Cheng Kuang TSO, Chou-Feng LEE, Chung-Hsiu CHENG, Jr-Sheng CHEN, Chun Yan CHEN, Chih-Hsien HSU, Chin-Tai HUNG
  • Publication number: 20230051164
    Abstract: A fitting for an upper brush in a double brush scrubbing chamber of a wafer cleaning system is disclosed. The fitting includes a base plate, a flanged pipe, and a threaded connector. The base plate includes a threaded hole with a stop surface therein and a channel extending from the stop surface through a lower surface of the base plate. The flanged pipe is inserted into the base plate such that the flange at the top end of a hollow tube rests on the stop surface and the hollow tube passes through the channel of the base plate. The threaded connector has a passage therethrough, and engages the threaded hole of the base plate to fix the flanged pipe in place. This structure is able to provide fluid while minimizing particle generation.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 16, 2023
    Inventors: Cheng-Ping Chen, Ping-Shen Chou, Tsung-Lung Lai, Ching-Wen Cheng, Chun Yan Chen
  • Publication number: 20230042074
    Abstract: A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.
    Type: Application
    Filed: February 9, 2022
    Publication date: February 9, 2023
    Inventors: Chia-Cheng Tsai, Kuo-Hsin Ku, Chien-Wei Chang, Chun Yan Chen, Chia-Chi Chung
  • Publication number: 20230009839
    Abstract: A system and method for chemical mechanical polishing (“CMP”) pad replacement on a CMP processing tool. A platen carrier having two or more platens is positioned within a platen cleaning process module. Each platen includes a CMP pad affixed thereto, and is capable of being independently rotated during operations. When a pad requires replacement, the platen carrier rotates towards a pad tearer tool, which extends and pivots to remove the used pad from the platen as the carrier rotates. A pad tape replacement module is positioned above the CMP tool with pad tape extending from a supply roll to a recycle roll. As the pad tape transits through the module, a backing of the tape is separated and recycled. A pad disposed in the pad tape is then applied to a platen via a pressure roller.
    Type: Application
    Filed: January 20, 2022
    Publication date: January 12, 2023
    Inventors: Shih-Chung Chen, Wei-Kang Tu, Ching-Wen Cheng, Chun Yan Chen
  • Publication number: 20220395512
    Abstract: Compounds of general formula (I): wherein R1, R2, R3, R4, R5a, R5b X1, X2, Z and Y are as defined herein are positive modulators of the calcium-activated chloride channel (CaCC), TMEM16A. The compounds are useful for treating diseases and conditions affected by modulation of TMEM16A, particularly respiratory diseases and conditions.
    Type: Application
    Filed: May 17, 2022
    Publication date: December 15, 2022
    Inventors: Stephen Collingwood, Clive Mccarthy, Jonathan David Hargrave, Duncan Alexander Hay, Thomas Beauregard Schofield, Sarah Ellam, Craig Stephen Buxton, Matthew Habgood, Peter Neville Ingram, Chun Yan Ma, Spencer Charles Robert Napier, Abdul Kadar Shaikh, Matthew Raymond Smith, Christopher Charles Stimson, Edward Richard Walker
  • Publication number: 20220359165
    Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Jr-Sheng CHEN, An-Chi LI, Shi-Che HUANG, Chih-Hsien HSU, Zhi-Hao HUANG, Ming Chih WANG, Yu-Pei CHIANG, Chun Yan CHEN
  • Publication number: 20220359168
    Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Jr-Sheng CHEN, An-Chi LI, Shih-Che HUANG, Chih-Hsien HSU, Zhi-Hao HUANG, Alex WANG, Yu-Pei CHIANG, Chun Yan Chen