Patents by Inventor Chun Yan

Chun Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10115607
    Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 30, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Chun Yan, Hua Chung, Schubert S. Chu
  • Patent number: 10090147
    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 2, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Chun Yan, Xinyu Bao, Melitta Manyin Hon, Hua Chung, Schubert S. Chu
  • Publication number: 20180277649
    Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.
    Type: Application
    Filed: March 22, 2018
    Publication date: September 27, 2018
    Inventors: Zhiyuan YE, Xinyu BAO, Chun YAN, Hua CHUNG, Schubert S. CHU, Satheesh KUPPURAO
  • Patent number: 10043667
    Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing. In one implementation, the method includes removing oxides from an exposed surface of a substrate in an inductively coupled plasma chamber, forming an epitaxial layer on the exposed surface of the substrate in an epitaxial deposition chamber, and performing an outgassing control of the substrate by subjecting the substrate to a first plasma formed from a first etch precursor in the inductively coupled plasma chamber at a first chamber pressure, wherein the first etch precursor comprises a hydrogen-containing precursor, a chlorine-containing precursor, and an inert gas, and subjecting the substrate to a second plasma formed from a second etch precursor in the inductively coupled plasma chamber at a second chamber pressure that is higher than the first chamber pressure, wherein the second etch precursor comprises a hydrogen-containing precursor and an inert gas.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao, Hua Chung, Schubert S. Chu
  • Publication number: 20180213520
    Abstract: In accordance with an example embodiment of the present invention, a method comprises allocating a control channel resource in a wireless relay transmission frame on a wireless relay link; generating a control signaling based on at least one of a resource allocation scheme, a status of the wireless relay link and a traffic condition of the wireless relay link; mapping the control signaling to the allocated control channel resource via at least one of a time-first mapping, a frequency-first mapping, and a multiplexing mapping; and transmitting the control signaling in the allocated control channel resource on the wireless relay link to at least one associated relay node.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 26, 2018
    Applicant: Wireless Future Technologies Inc.
    Inventors: Erlin Zeng, Hai Ming Wang, Xiangguang Che, Chun Yan Gao, Peng Chen, Jing Han, Bernhard Raaf
  • Publication number: 20180211836
    Abstract: The present disclosure generally relates to a device having a thin, low-defect, fully-relaxed silicon germanium (SiGe) layer, and methods of manufacture thereof. The methods generally include depositing a silicon oxide layer on a silicon layer, patterning the silicon oxide layer, exposing the silicon oxide layer to an etchant to form one or more recesses in the silicon layer and one or more faceted silicon oxide caps, and epitaxially growing a silicon germanium layer in the one or more recesses and over an apex of the one or more faceted silicon oxide caps. The device generally includes a silicon layer having one or more recesses defining one or more vertical extensions, one or more faceted silicon oxide caps on the one or more vertical extensions, and a silicon germanium layer in the one or more recesses and extending over an apex of the one or more faceted silicon oxide caps.
    Type: Application
    Filed: July 18, 2017
    Publication date: July 26, 2018
    Inventors: Chun YAN, Xinyu BAO, Yi-Chiau HUANG, Hua CHUNG, Schubert S. CHU
  • Publication number: 20180174825
    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 21, 2018
    Inventors: Chun YAN, Xinyu BAO, Melitta Manyin HON, Hua CHUNG, Schubert S. CHU
  • Patent number: 10002759
    Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes applying a passivating agent containing antimony to portions of a silicon substrate exposed through trenches formed in a dielectric layer on the silicon substrate, while applying the passivating agent containing antimony, exposing the silicon substrate to a group IV-containing precursor to form an epitaxial layer having a V-shaped structure having an exposed (111) plane at a bottom of the trenches, and forming a semiconductor layer on the epitaxial layer.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 19, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Chun Yan, Errol Antonio C. Sanchez
  • Patent number: 9998258
    Abstract: A method of transmitting uplink control signals/status bits from a user equipment, said user equipment having multiple transmit antennae, and said control signals correspond to a plurality of previous downlink transmissions, wherein said control signals are transmitted over a plurality of PUCCH resources and over said multiple antennae, and transmitted during a single uplink sub-frame. Use of multiple PUCCH resources and multiple antennae allow greater spatial diversity.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: June 12, 2018
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Esa Tapani Tiirola, Kari Pekka Pajukoski, Kari Juhani Hooli, Peng Chen, Chun Yan Gao
  • Patent number: 9989827
    Abstract: A display device is provided. The display device includes a base; a gate conductor disposed directly on the base and including a gate line and a gate electrode; a gate insulating layer disposed on the gate conductor and including an overlap portion, which overlaps with the gate conductor, and a non-overlap portion, which is connected to the overlap portion, does not overlap with the gate conductor, and is spaced apart from the base; and a semiconductor pattern disposed on the gate insulating layer and overlapping with the gate electrode, wherein edges of the gate insulating layer project further than edges of the gate conductor and edges of the semiconductor pattern.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: June 5, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Jae Jeon, Il You, Seung Rae Kim, Chun Yan Jin, Beom Soo Park, Jae Hyun Park, Sang Ju Lee, Hye Won Hyeon
  • Publication number: 20180138032
    Abstract: Embodiments described herein generally relate to improved methods and solutions for cleaning a substrate prior to epitaxial growth of Group III-V channel materials. A first processing gas, which includes a noble gas and a hydrogen source, is used to remove the native oxide layer from the substrate surface. A second processing gas, Ar/Cl2/H2, is then used to create a reactive surface layer on the substrate surface. Finally, a hydrogen bake with a third processing gas, which includes a hydrogen source and an arsine source, is used to remove the reactive layer from the substrate surface.
    Type: Application
    Filed: January 15, 2018
    Publication date: May 17, 2018
    Inventors: Chun YAN, Xinyu BAO
  • Patent number: 9936484
    Abstract: In accordance with an example embodiment of the present invention, a method comprises allocating a control channel resource in a wireless relay transmission frame on a wireless relay link; generating a control signaling based on at least one of a resource allocation scheme, a status of the wireless relay link and a traffic condition of the wireless relay link; mapping the control signaling to the allocated control channel resource via at least one of a time-first mapping, a frequency-first mapping, and a multiplexing mapping; and transmitting the control signaling in the allocated control channel resource on the wireless relay link to at least one associated relay node.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 3, 2018
    Assignee: WIRELESS FUTURE TECHNOLOGIES, INC.
    Inventors: Erlin Zeng, Hai Ming Wang, Xiangguang Che, Chun Yan Gao, Peng Chen, Jing Han, Bernhard Raaf
  • Publication number: 20180082836
    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
    Type: Application
    Filed: January 27, 2017
    Publication date: March 22, 2018
    Inventors: Chun YAN, Xinyu BAO, Melitta Manyin HON, Hua CHUNG, Schubert S. CHU
  • Publication number: 20180082874
    Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: Xinyu BAO, Chun YAN, Hua CHUNG, Schubert S. CHU
  • Publication number: 20180082835
    Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing of hazardous gasses after an epitaxial process. In one implementation, the method includes providing a substrate comprising an epitaxial layer into a transfer chamber, wherein the transfer chamber has an ultraviolet (UV) lamp module disposed adjacent to a top ceiling of the transfer chamber, flowing an oxygen-containing gas into the transfer chamber through a gas line of the transfer chamber, flowing a non-reactive gas into the transfer chamber through the gas line of the transfer chamber, activating the UV lamp module to oxidize residues or species on a surface of the substrate to form an outgassing barrier layer on the surface of the substrate, ceasing the flow of the oxygen-containing gas and the nitrogen-containing gas into the transfer chamber, pumping the transfer chamber, and deactivating the UV lamp module.
    Type: Application
    Filed: January 27, 2017
    Publication date: March 22, 2018
    Inventors: Chun YAN, Xinyu BAO, Hua CHUNG, Schubert S. CHU
  • Publication number: 20180073162
    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More specifically, implementations disclosed herein relate to apparatus, systems, and methods for reducing substrate outgassing. A substrate is processed in an epitaxial deposition chamber for depositing an arsenic-containing material on a substrate and then transferred to a degassing chamber for reducing arsenic outgassing on the substrate. The degassing chamber includes a gas panel for supplying hydrogen, nitrogen, and oxygen and hydrogen chloride or chlorine gas to the chamber, a substrate support, a pump, and at least one heating mechanism. Residual or fugitive arsenic is removed from the substrate such that the substrate may be removed from the degassing chamber without dispersing arsenic into the ambient environment.
    Type: Application
    Filed: January 24, 2017
    Publication date: March 15, 2018
    Inventors: Xinyu BAO, Chun YAN, Hua CHUNG, Schubert S. CHU
  • Publication number: 20180076031
    Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing. In one implementation, the method includes removing oxides from an exposed surface of a substrate in an inductively coupled plasma chamber, forming an epitaxial layer on the exposed surface of the substrate in an epitaxial deposition chamber, and performing an outgassing control of the substrate by subjecting the substrate to a first plasma formed from a first etch precursor in the inductively coupled plasma chamber at a first chamber pressure, wherein the first etch precursor comprises a hydrogen-containing precursor, a chlorine-containing precursor, and an inert gas, and subjecting the substrate to a second plasma formed from a second etch precursor in the inductively coupled plasma chamber at a second chamber pressure that is higher than the first chamber pressure, wherein the second etch precursor comprises a hydrogen-containing precursor and an inert gas.
    Type: Application
    Filed: January 27, 2017
    Publication date: March 15, 2018
    Inventors: Chun YAN, Xinyu BAO, Hua CHUNG, Schubert S. CHU
  • Patent number: 9905412
    Abstract: Embodiments described herein generally relate to improved methods and solutions for cleaning a substrate prior to epitaxial growth of Group III-V channel materials. A first processing gas, which includes a noble gas and a hydrogen source, is used to remove the native oxide layer from the substrate surface. A second processing gas, Ar/Cl2/H2, is then used to create a reactive surface layer on the substrate surface. Finally, a hydrogen bake with a third processing gas, which includes a hydrogen source and an arsine source, is used to remove the reactive layer from the substrate surface.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 27, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chun Yan, Xinyu Bao
  • Publication number: 20180052711
    Abstract: The disclosure discloses a method and system for scheduling a video analysis task. The method includes: the video analysis task which is received is evaluated, and then is issued to a cluster for execution (S1); an execution state of the video analysis task is monitored in real time, and whether the video analysis task is required to be dynamically regulated or not is determined (S2); and allocated resources are regulated for the video analysis task, according to a priority of the video analysis task, when the video analysis task is required to be dynamically regulated (S3). Resource allocation for the tasks is automatically regulated to implement automatic and reasonable integration and full utilization of the resources, automatic load balancing is implemented.
    Type: Application
    Filed: December 22, 2015
    Publication date: February 22, 2018
    Inventors: Mingyao Zhou, Shiliang Pu, Chun Yan, Xin Li, Jinquan Tang
  • Publication number: 20180033872
    Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.
    Type: Application
    Filed: January 27, 2017
    Publication date: February 1, 2018
    Inventors: Xinyu BAO, Chun YAN, Errol Antonio C. SANCHEZ, Hua CHUNG