Patents by Inventor Chun Yang

Chun Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194682
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Application
    Filed: January 22, 2024
    Publication date: June 13, 2024
    Applicant: Tiawan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien WU, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Publication number: 20240196537
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a base, a semiconductor package, and a capacitor. The base has a top surface and a bottom surface. The semiconductor package is disposed on the top surface of the base. The capacitor is disposed on the semiconductor package and located between the semiconductor package and the base. The capacitor has a back surface located away from the semiconductor package. The back surface of the capacitor is higher than the bottom surface of the base and lower than the top surface of the base.
    Type: Application
    Filed: November 16, 2023
    Publication date: June 13, 2024
    Inventors: Hui-Chi TANG, Pei-San CHEN, Shao-Chun HO, Bo-Jiun YANG
  • Patent number: 12009033
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Publication number: 20240186459
    Abstract: A light emitting structure includes a carrying unit, a light emitting unit and a light transmitting unit. The light emitting unit is arranged on the carrying unit, and includes a light emitting surface. The light transmitting unit directly contacts the light emitting unit, and includes a first surface and a second surface opposite to each other. The first surface covers at least part of the light emitting surface, and the second surface directly contacts a gas.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 6, 2024
    Inventors: Chen-Lun HSING CHEN, Jung-Hao HUNG, Yung-Chun YANG
  • Publication number: 20240183082
    Abstract: A method for manufacturing an elastic fiber and the elastic fiber are provided. The method includes: providing a thermoplastic polyester elastomer; drying the thermoplastic polyester elastomer; melting the thermoplastic polyester elastomer by an extruder to form a melt; extruding the melt by a spinneret plate to form a plurality of filamentous streams; feeding the filamentous streams into a spinning channel for cooling and curing to form a plurality of monofilaments; and bundling and oiling the monofilaments by an oil wheel, after extending and guiding the monofilaments by a first godet roller and a second godet roller, and winding the monofilaments by a winder to obtain a thermoplastic polyester elastic fiber.
    Type: Application
    Filed: October 27, 2023
    Publication date: June 6, 2024
    Inventors: CHIH-YI LIN, KUO-KUANG CHENG, LI-YUAN CHEN, CHI-WEI CHANG, CHIA-CHUN YANG
  • Publication number: 20240182456
    Abstract: The present invention relates to compounds of formula (I) as activators of glucagon-like peptide 1 (GLP1) receptor for the treatment of obesity, type 2 diabetes mellitus, insulin resistance, hyperinsulinemia, glucose intolerance, hyperglycemia, one or more diabetic complications, diabetic nephropathy, dyslipidemia, non-alcoholic fatty liver disease (NAFLD), non-alcoholic steatohepatitis (NASH), hypertension, atherosclerosis, peripheral arterial disease, stroke, cardiomyopathy, atrial fibrillation, heart failure, coronary heart disease and neuropathy. Preferred compounds are e.g. 2-((4-((S)-2-(4-chloro-2-fluorophenyl)-2-methylbenzo[d][1,3]dioxol-4-yl)piperidin-1-yl)methyl)-1-(((S)-oxetan-2-yl)methyl)-1H-imidazole derivatives and similar compounds, such as e.g. C-1, C-2, C-3, C-4 and other compounds.
    Type: Application
    Filed: April 11, 2022
    Publication date: June 6, 2024
    Inventors: Martin ALLAN, Matthew CARSON, Thomas CAYA, Lara CZABANIUK, Ming QIAN, Daniel SMITH, Troy SMITH, Liansheng SU, Chung-Yeh WU, Lihua YANG, Chun ZHANG, Ping ZHANG, Xilin ZHOU
  • Patent number: 12002761
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: June 4, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Patent number: 11998613
    Abstract: The present disclosure provides an immunoconjugate includes an antibody comprising an antigen-binding fragment that specifically binds to an epitope in mesothelin, N-glycan binding domain and an N-glycan; a linker linking to the N-glycan; and a payload A and a payload B conjugated to the linker, respectively; wherein the payload A and the payload B are the same or different. A pharmaceutical composition comprises the immunoconjugate and a method for treating cancer are also provided in the disclosure.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: June 4, 2024
    Assignee: DEVELOPMENT CENTER FOR BIOTECHNOLOGY
    Inventors: Shih-Hsien Chuang, Wei-Ting Sun, Ying-Shuan Lailee, Chun-Liang Lai, Wun-Huei Lin, Win-Yin Wei, Shih-Chong Tsai, Cheng-Chou Yu, Chao-Yang Huang
  • Publication number: 20240175162
    Abstract: Provided is a roughened copper foil capable of achieving both excellent transmission characteristics and suppression of powdering. This roughened copper foil includes a roughened surface on at least one side. The roughened surface has a roughness slope tan ? of 0.58 or less as calculated based on a mean height Rc (?m) and a mean width RSm (?m) of profile elements by formula Rc/(0.5×RSm), and a sharpness index Rc×Sku of 2.35 or less that is a product of the mean height Rc (?m) and a kurtosis Sku. Rc and RSm are values measured in accordance with JIS B0601-2013 under a condition of not performing a cutoff by a cutoff value ?s and a cutoff value ?c, and Sku is a value measured in accordance with ISO 25178 under a condition of not performing a cutoff using an S filter and an L filter.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 30, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Ayumu TATEOKA, Tsubasa KATO, Shota KAWAGUCHI, Po Chun YANG
  • Publication number: 20240167756
    Abstract: A refrigerator includes a refrigerator body and a door body. In a case where the door body is opened from a closed state to a first state, a first hinge shaft moves from a first positioning position to a second positioning position along a first positioning trajectory line with respect to a first trajectory slot, and a second hinge shaft moves from a first guiding position to a second guiding position along a first guiding trajectory line with respect to a second trajectory slot. In a case where the door body continues to be opened from the first state to a second state, the first hinge shaft moves from the second positioning position to a third positioning position along a second positioning trajectory line, the second hinge shaft moves from the second guiding position to a third guiding position along a second guiding trajectory line.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 23, 2024
    Applicant: HISENSE REFRIGERATOR CO., LTD.
    Inventors: Chun YANG, Yufeng BAO, Xiangping ZHANG, Haiyan WANG, Dong GUO
  • Publication number: 20240164051
    Abstract: A fan module is adapted to be disposed on a mainboard. The fan module includes a base, a stator unit, a circuit board, a first restriction structure and a second restriction structure. The base includes a mounting shaft and a base opening, wherein the mounting shaft has an axis. The mounting shaft is telescoped in the stator unit. The circuit board is coupled to the stator unit, wherein the circuit board includes a circuit board connection port. The first restriction structure restricts the circuit board, wherein the first restriction structure is arranged on the first straight line, and the first restriction structure is disposed a first distance away from the axis. The second restriction structure restricts the circuit board, wherein the second restriction structure is arranged on the second straight line, the second restriction structure is disposed a second distance away from the axis.
    Type: Application
    Filed: June 12, 2023
    Publication date: May 16, 2024
    Inventors: Kuo-Tung HSU, Wen-Chun HSU, Chao-Fu YANG, Shuo-Sheng HSU
  • Publication number: 20240156440
    Abstract: A method of reconstructing transcranial images using a dual-mode ultrasonic phased array includes steps of: controlling channels to emit energy toward an intracranial target point of a patient; respectively generating backscattered radiofrequency (RF) data by using the channels to receive backscattered energy reflected from the intracranial target; and reconstructing an acoustic distribution image based on those backscattered RF data in real-time. Compared with Pre-Treatment Ray Tracing Method, the present invention can display intracranial pressure distribution in real-time; compared with MR Thermometry, the present invention can be applied to low-energy applications without temperature change; and compared with Passive Cavitation Imaging, the present invention can stably present acoustic distribution images without relying on microbubbles.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: HAO-LI LIU, HSIANG-CHING LIN, ZHEN-YUAN LIAO, HSIANG-YANG MA, CHIH-HUNG TSAI, CHUN-HAO CHEN
  • Publication number: 20240162093
    Abstract: A method for fabricating semiconductor device includes first providing a substrate having a core region, a LNA region, a I/O region, and a PA region, forming a first gate structure on the LNA region, a second gate structure on the PA region, a third gate structure on the core region, and a fourth gate structure on the I/O region, forming an interlayer dielectric (ILD) layer on the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, and then forming a first hard mask on the first gate structure and a second hard mask on the second gate structure. Preferably, a width of the first hard mask is greater than a width of the first gate structure.
    Type: Application
    Filed: December 13, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Chun Chang, Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 11982611
    Abstract: A method includes providing a cartridge and the cartridge includes a slot for receiving a microfluidic chip having a set of first channels. The cartridge also includes a set of second channels and each channel of the set of second channels is coupleable to a different channel of the set of first channels during use with the microfluidic chip. The cartridge also includes an indent configured for engagement and alignment of the cartridge during use. The method also includes inserting the cartridge into a device, such that the cartridge engages a first biasing member of the device configured for alignment of the cartridge in a first direction. The first biasing member is configured to bias movement of the cartridge into locking position with a notch of the device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: May 14, 2024
    Assignee: NANOCELLECT BIOMEDICAL, INC.
    Inventors: Sunghwan Cho, Jose Manuel Morachis, Ivan Gagne, Rick Segil, William Arthur Alaynick, Zhe Mei, Sean Phillips, Chien-Chun Yang, Dongseob Yun, Michael Jerome Benchimol, Manna Doud, Nicholas Sullivan, Constance Ardila
  • Patent number: 11983479
    Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Publication number: 20240153949
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • Publication number: 20240151814
    Abstract: The present disclosure provides a radar object recognition method, which includes steps as follows. The radar image generation is performed on radar data to generate a radar image; the radar image is inputted into an object recognition model, so that the object recognition model outputs a recognition result; the post-process is performed on the recognition result to eliminate recognition errors from the recognition result.
    Type: Application
    Filed: February 21, 2023
    Publication date: May 9, 2024
    Inventors: Ta-Sung LEE, Ming-Chun LEE, Tai-Yuan HUANG, Chia-Hsing YANG
  • Patent number: 11978392
    Abstract: A precharge method for a data driver includes steps of: outputting a display data to a plurality of output terminals of the data driver; outputting a second precharge voltage to an output terminal among the plurality of output terminals prior to outputting the display data to the output terminal, to precharge the output terminal to a voltage level closer to an output voltage; and outputting a first precharge voltage to the output terminal prior to outputting the second precharge voltage. The first precharge voltage provides a faster voltage transition on the output terminal than the second precharge voltage.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: May 7, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Min-Yang Chiu, Yu-Sheng Ma, Jin-Yi Lin, Hsuan-Yu Chen, Jhih-Siou Cheng, Chun-Fu Lin
  • Patent number: 11976990
    Abstract: A force sensing method, applied to a force sensing system comprising a plurality of force sensors and a touch sensing surface, comprising: (a) determining a first location of a first object on the touch sensing surface; (b) defining a first force sensing region according to the first location; and (c) computing a first system sensing force which the first object causes to the touch sensing surface according to the first location, and according to at least one sensor sensing force of a first part of the force sensors corresponding to the first force sensing region. The present invention also discloses a force sensing system which uses the above-mentioned force sensing method, and an efficient force sensor calibration method. Noises can be reduced and power consumption can be decreased, since only sensor sensing forces of force sensors near the object are used for computing the system sensing force.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 7, 2024
    Assignee: PixArt Imaging Inc.
    Inventors: Ming-Hung Tsai, Chun-Yang Chen, Yen-Po Chen
  • Publication number: 20240145498
    Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.
    Type: Application
    Filed: January 4, 2023
    Publication date: May 2, 2024
    Inventors: Hao-Lin Yang, Fu-Sheng Kuo, Ching-Chun Wang, Hsiao-Hui Tseng, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung