Abstract: Provided is a device including a fin structure and methods for forming such a device. A method includes forming an initial fin having a sidewall. Further, the method includes forming an additional layer of fin material over the sidewall, wherein the additional layer has a thickness. Also, the method includes adjusting the thickness of the additional layer of fin material to form a fin structure with a desired critical dimension.

Abstract: A case for receiving at least one electronic device is provided, including a housing, a hinge, a locking member, and a cover. The housing has an accommodating space and an opening communicated with the accommodating space. The hinge is slidably connected to the housing. The cover has an upper side, a lower side, and an outer surface. The lower side is pivotally connected to the hinge. When the locking member affixes the upper side to the housing and the hinge is in a first position relative to the housing, the cover is disposed between an environment space and the accommodating space, and the outer surface faces the environment space. When the locking member is released and the hinge moves to a second position relative to the housing, the cover leaves the position between the environment space and the accommodating space, and the outer surface faces the environment space.

Abstract: An electronic device includes a first substrate; a second substrate arranged opposite to the first substrate; a first electrode layer disposed on the first substrate; a display medium layer disposed between the first electrode layer and the second substrate; and a first metal element, wherein the first metal element is fixed on the first electrode layer through a conductive glue and an insulating glue; wherein in a normal direction of the first substrate, the conductive glue and the insulating glue are overlapped.

Abstract: A manufacturing method of an elastic paint is provided. The manufacturing method includes: blending an original composition to produce a first rough painting material, where the original composition includes polycarbonatediol (PCDL), a polyurethane (PU) elastic powder, poly(methyl methacrylate) (PMMA), a photoinitiator, a wetting agent, a solvent, and an auxiliary agent; carrying out precipitation treatment on the first rough painting material, and filtering the treated first rough painting material, to produce a second rough painting material; blending the second rough painting material; sealing the blended second rough painting material to produce a plurality of layers in the second rough painting material; removing an upper portion and a lower portion from the layers to produce a main ingredient; and adding a curing agent and a diluent into the main ingredient to produce an elastic paint.

Abstract: A semiconductor package according to the present disclosure includes a routing structure, a first die and a second die disposed over the routing structure, a first array of contact features disposed along a first direction and electrically coupling the first die to the routing structure, and a second array of contact features disposed along the first direction and electrically coupling the second die to the routing structure. The routing structure includes a plurality of metal lines and each of the plurality of metal lines electrically connects one of the first array of contact features and one of the second array of contact features. Each of the plurality of metal lines comprises at least two 90-degree turns on a horizontal plane.

Abstract: A charging system includes a source terminal and a sink terminal. The control method of the charging system includes transmitting a bus voltage by the source terminal, determining whether the sink terminal has entered a sink attached state when the sink terminal receives the bus voltage, enabling a message transceiver of the sink terminal if the sink terminal has entered the sink attached state, transmitting a source message to the transceiver of the sink terminal by the source terminal, transmitting a request message to the source terminal by the message transceiver of the sink terminal while the source terminal transmits the source message, and continuing to enable a communication function for communicating with the sink terminal and continuing to transmit the bus voltage to the sink terminal by the source terminal when the source terminal receives the request message.

Abstract: A cleaning apparatus, method, and dry chamber are provided for cleaning a wafer carrier that holds wafers as part of a semiconductor fabrication process. The cleaning apparatus includes a wet chamber that receives the wafer carrier to be washed and a reservoir in fluid communication with the wet chamber. The reservoir stores a cleaning liquid that is introduced to the wafer carrier within the wet chamber during a washing operation, and a dry chamber is spaced apart from the wet chamber. The dry chamber receives the wafer carrier after the wafer carrier is washed in the wet chamber and holds the wafer carrier during a drying operation. A transport system transports the wafer carrier between the wet chamber and the dry chamber during a cleaning process.

Abstract: A first die includes a first substrate and a first interconnect structure. A second die is bonded to the first die and includes a second substrate and a second interconnect structure, such that the first and second interconnect structures are arranged between the first and second substrates. A redistribution layer (RDL) stack is arranged on an outer side of the first die opposite the first interconnect structure. A heat path includes a through substrate via (TSV) extending from a conductive layer in the first interconnect structure, through the first substrate, and into the RDL stack. An RDL dielectric material is included in the RDL stack and separates the heat path from an ambient environment. A thermal conductivity of the RDL dielectric is over twenty times a thermal conductivity of an interconnect dielectric material of the first interconnect structure or of the second interconnect structure.

Abstract: A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

Abstract: A cleaning apparatus, method, and dry chamber are provided for cleaning a wafer carrier that holds wafers as part of a semiconductor fabrication process. The cleaning apparatus includes a wet chamber that receives the wafer carrier to be washed and a reservoir in fluid communication with the wet chamber. The reservoir stores a cleaning liquid that is introduced to the wafer carrier within the wet chamber during a washing operation, and a dry chamber is spaced apart from the wet chamber. The dry chamber receives the wafer carrier after the wafer carrier is washed in the wet chamber and holds the wafer carrier during a drying operation. A transport system transports the wafer carrier between the wet chamber and the dry chamber during a cleaning process.

Abstract: A die stacking structure, a semiconductor package and a method for manufacturing the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; a gap profile modifier, laterally enclosing bottommost portions of the second device dies, wherein a thickness of the gap profile modifier gradually decreases away from sidewalls of the second device dies; and a dielectric material, covering the gap profile modifier and laterally surrounding the second device dies.

Abstract: A sensor is provided, including a substrate, a chip and a sensing element. The substrate has a plate-like shape and includes a surface and an interconnect structure disposed in the substrate. The chip is embedded in the substrate and is electrically connected to the interconnect structure. The sensing element is disposed on the surface of the substrate, and is electrically connected to the chip through the interconnect structure.

Abstract: A surge protection apparatus includes a chassis, a surge circuit breaker, and a surge protection module. The chassis has an accommodating space and an opening, and the opening is communicated with the accommodating space. The surge circuit breaker is disposed in the accommodating space. The surge protection module is configured to be electrically connected to a second connector in the chassis, and the second connector is electrically connected to the surge circuit breaker. The surge protection module extends in a first axis, and the surge protection module is plugged in or pulled out of the chassis through the opening along the first axis. The surge protection module includes a first connector detachably connected to the second connector.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: Provided is an epitaxial structure and a method for forming such a structure. The method includes forming a fin structure on a substrate, wherein the fin structure includes a semiconductor material having substantially a {110} crystallographic orientation. The method includes etching a portion of the fin structure to expose a sidewall portion of the semiconductor material. Further, the method includes growing an epitaxial structure on the sidewall of the semiconductor material, wherein the epitaxial structure propagates with facets having a {110} crystallographic orientation.

Abstract: A cleaning apparatus, method, and dry chamber are provided for cleaning a wafer carrier that holds wafers as part of a semiconductor fabrication process. The cleaning apparatus includes a wet chamber that receives the wafer carrier to be washed and a reservoir in fluid communication with the wet chamber. The reservoir stores a cleaning liquid that is introduced to the wafer carrier within the wet chamber during a washing operation, and a dry chamber is spaced apart from the wet chamber. The dry chamber receives the wafer carrier after the wafer carrier is washed in the wet chamber and holds the wafer carrier during a drying operation. A transport system transports the wafer carrier between the wet chamber and the dry chamber during a cleaning process.

Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract: A light-emitting element panel, including a temporary storage substrate, an auxiliary pattern layer, multiple adhesive patterns, and multiple light-emitting elements, is provided. The auxiliary pattern layer is disposed on the temporary storage substrate and has multiple openings. The adhesive patterns are respectively disposed in the openings of the auxiliary pattern layer. The light-emitting elements are respectively disposed on the adhesive patterns. A reaction rate of the auxiliary pattern layer to a laser is lower than a reaction rate of the adhesive pattern to the laser. Moreover, another light-emitting element panel is also provided.

Abstract: A device includes a first nanostructure over a substrate and a first source/drain region adjacent the first nanostructure. The first source/drain region includes a first epitaxial layer covering a first sidewall of the first nanostructure. The first epitaxial layer has a first concentration of a first dopant. The first epitaxial layer has a round convex profile opposite the first sidewall of the first nanostructure in a cross-sectional view. The first source/drain region further includes a second epitaxial layer covering the round convex profile of the first epitaxial layer in the cross-sectional view. The second epitaxial layer has a second concentration of the first dopant, the second concentration being different from the first concentration.