Abstract: A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

Abstract: A method of making a semiconductor device includes: (a) providing a semiconductor substrate that is made from a material containing an element of boron group; (b) forming on the semiconductor substrate a buffer structure that includes an aluminum nitride buffer film formed using a physical vapor deposition technique; and (c) forming on the buffer structure a semiconductor unit that includes a GaN-based epitaxial layer, the GaN-based epitaxial layer having a hexagonal crystal structure and being formed using a chemical vapor deposition technique.

Abstract: A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.

Abstract: A dynamic random access memory (DRAM) and a manufacturing method thereof are disclosed. A storage cell of the DRAM includes a FINFET and a capacitor. A gate of the FINFET is formed by a metal nitride or a carbonized metal having the effect of stress-induced strain. A gate dielectric of the FINFET and/or a dielectric of the capacitor can be formed by a ferroelectric material having negative capacitance characteristics. A strained-gate engineering is used in the invention achieve effects of (1) increasing ferro-electricity of the dielectric to enhance the operation speed and endurance of the FINFET; and (2) enhancing the ferro negative capacitance effect to improve the sub-threshold swing of the FINFET, so that the switching power and the off-current of the FINFET can be reduced and the charge retention capability of capacitor can be effectively enhanced to improve the operation characteristics of the DRAM.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a source and a drain, a p-type nitride layer and a strain gate. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source and the drain are respectively disposed at two sides of the barrier layer. The p-type nitride layer is disposed on the barrier layer. The strain gate is disposed over the p-type nitride layer for tuning a first strain of the channel layer and a second strain of the barrier layer.

Abstract: A magnetic capacitor includes a first electrode layer formed by depositing a first conducting material including graphene, a second electrode layer formed by depositing a second conducting material including graphene, and an insulator layer located between the first electrode layer and the second electrode layer. The magnetic capacitor further includes a first magnetized layer that includes one or more first ferro-magnetic elements that are magnetized to apply a first magnetic field to the insulator layer, and a second magnetized layer that includes one or more second ferro-magnetic elements that are magnetized to apply a second magnetic field to the insulator layer. The insulator layer is located between the first magnetized layer and the second magnetized layer. The first magnetic field and the second magnetic field improve a first electrical property of the magnetic capacitor.

Abstract: A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.

Abstract: A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.

Abstract: A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.

Abstract: The invention discloses a social networking system which includes a main data processing apparatus, a plurality of smart clothing apparatus and a plurality of sub-data-processing apparatuses. Each smart clothing apparatus includes a light-emitting device assembly. Each sub-data-processing apparatus corresponds to one of the smart clothing apparatuses. The main data processing apparatus transmits an inquiry information to each sub-data-processing apparatus. The inquiry information includes a plurality of selection data and a plurality of light color data. Each selection datum corresponds to one of the light color data. Each sub-data-processing apparatus receives the inquiry information, displays the plurality of selection data, and transmits, responsive to a selection signal corresponding to one of the selection data, the light color datum corresponding to said one selection datum to the corresponding smart clothing apparatus.

Abstract: A semiconductor device for ultra-high voltage (UHV) operation disclosed in the present invention includes a substrate having a normally-on channel, a negative capacitance material layer, an electrode, a source and a drain. The negative capacitance material layer is disposed over the substrate and capable of adjusting the threshold voltage of the semiconductor device so as to transform the normally-on channel into a normally-off channel and change the transistor characteristics of the semiconductor device from a depletion mode to an enhance mode. In addition, the semiconductor device also includes a gate dielectric layer made of high-k material between the negative capacitance material layer, a gate layer between the gate dielectric layer and the negative capacitance material layer and an ion implantation layer in the substrate under the gate. Furthermore, the aforementioned technical features or structures can be formed in a semiconductor device having a gate-recessed structure.

Abstract: A silicon-controlled rectifier (SCR) includes a first-type field, a second-type first field and a second-type second field disconnectedly formed in a first-type well; an entire first-type doped region formed within the first-type field; a segmented second-type doped region formed within the second-type first field; and a segmented first-type doped region formed within the second-type second field.

Abstract: A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature.

Abstract: A magnetic capacitor includes a first electrode layer formed by depositing a first conducting material including graphene, a second electrode layer formed by depositing a second conducting material including graphene, and an insulator layer located between the first electrode layer and the second electrode layer. The magnetic capacitor further includes a first magnetized layer that includes one or more first ferro-magnetic elements that are magnetized to apply a first magnetic field to the insulator layer, and a second magnetized layer that includes one or more second ferro-magnetic elements that are magnetized to apply a second magnetic field to the insulator layer. The insulator layer is located between the first magnetized layer and the second magnetized layer. The first magnetic field and the second magnetic field improve a first electrical property of the magnetic capacitor.

Abstract: A light emitting device is provided. The light emitting device includes a substrate, an N type semiconductor layer formed on the substrate, an active layer, an electron-blocking layer, and a P type semiconductor layer formed on the electron-blocking layer. An N side electrode is formed on a first portion of the N type semiconductor layer, and the active layer is formed on a second portion of the N type semiconductor layer. The electron-blocking layer is a super lattice multi-layer structure formed on the active layer, the P type semiconductor layer is formed on the electron-blocking layer, and a P side electrode is formed on a portion of the P type semiconductor layer.

Abstract: An electronic system, an electronic apparatus, and an access authentication method thereof are provided. The electronic system includes a master apparatus and a slave apparatus. The slave apparatus is coupled to the master apparatus through a serial transmission interface. The slave apparatus includes a data storage unit protected by the slave apparatus with a predetermined key. The master apparatus sends an access request to the data storage unit through the serial transmission interface. The slave apparatus determines whether the master apparatus is allowed to access the data storage unit according to the predetermined key and a key inputted by the master apparatus for authentication.

Abstract: Present disclosure provides a method for manufacturing a semiconductor device array, including (1) providing a temporary substrate; (2) forming a plurality of discrete semiconductor structures over the temporary substrate; and (3) removing a surface portion of the temporary substrate to expose a peripheral bottom surface of the discrete semiconductor structure. Present disclosure also provides a method for transferring discrete semiconductor device, including (1) detaching discrete semiconductor structures of a first type from a first temporary substrate supporting the discrete semiconductor structures of the first type by a transfer stamp; (2) carrying the discrete semiconductor structures over a target substrate by the transfer stamp; and (3) dismounting the discrete semiconductor structures of the first type from the transfer stamp to predetermined sites on the target substrate.

Abstract: A method for fabricating a magnetic capacitor is provided. A first conducting material is deposited to form a first electrode layer. One or more first ferro-magnetic elements are deposited to form magnetic layer and are aligned and magnetized to produce a magnetic field. An insulating material is deposited to form an insulating layer. A second conducting material is deposited to form a second electrode layer. The one or more ferro-magnetic elements are aligned and magnetized to apply the magnetic field to the insulator layer so that the magnetic field is perpendicular to the first electrode layer and the second electrode layer, and so that the magnetic field is periodic along the length of the insulator layer and results in electric dipoles being formed in the insulator layer when a voltage is applied between the first electrode layer and the second electrode layer.

Abstract: A silicon-controlled rectifier (SCR) includes a first-type field, a second-type first field and a second-type second field disconnectedly formed in a first-type well; an entire first-type doped region formed within the first-type field; a segmented second-type doped region formed within the second-type first field; and a segmented first-type doped region formed within the second-type second field.

Abstract: A method of making a semiconductor device includes: (a) providing a semiconductor substrate that is made from a material containing an element of boron group; (b) forming on the semiconductor substrate a buffer structure that includes an aluminum nitride buffer film formed using a physical vapor deposition technique; and (c) forming on the buffer structure a semiconductor unit that includes a GaN-based epitaxial layer, the GaN-based epitaxial layer having a hexagonal crystal structure and being formed using a chemical vapor deposition technique.