Abstract: A method of forming laterally distributed light emitting diodes (LEDs) is disclosed. A first buffer layer with a first type of conductivity is formed on a semiconductor substrate, and a dielectric layer is formed on the first buffer layer. The dielectric layer is patterned to form a first patterned space therein, followed by forming a first active layer in the first patterned space. The dielectric layer is then patterned to form a second patterned space therein, followed by forming a second active layer in the second patterned space. Second buffer layers with a second type of conductivity are then formed on the first active layer and the second active layer. Finally, electrodes are formed on the second buffer layers and on the first buffer layer.

Abstract: A method of forming laterally distributed light emitting diodes (LEDs) is disclosed. A first buffer layer with a first type of conductivity is formed on a semiconductor substrate, and a dielectric layer is formed on the first buffer layer. The dielectric layer is patterned to form a first patterned space therein, followed by forming a first active layer in the first patterned space. The dielectric layer is then patterned to form a second patterned space therein, followed by forming a second active layer in the second patterned space. Second buffer layers with a second type of conductivity are then formed on the first active layer and the second active layer. Finally, electrodes are formed on the second buffer layers and on the first buffer layer.

Abstract: A backlight module and a liquid crystal display (LCD) both have a heat conductive structure for reducing the non-uniformity phenomenon of display. The backlight module comprises a frame, a reflective sheet, a heat-conductive plate, and a circuit board, wherein the frame has a bottom portion and at least one substantially step-typed through hole is formed therein. The reflective sheet is disposed on the inner surface of the bottom portion, and the heat-conductive plate is disposed in the step-typed through hole, and is spaced from the reflection sheet at a predetermined distance. The circuit board is disposed on the outer surface of the bottom portion of the frame, and has at least one electrical component that is received in the substantially step-typed through hole.

Abstract: A light emitting device (LED) structure formed on a Group IV-based semiconductor substrate is provided. The LED structure includes a Group IV-based substrate, an AlN nucleation layer formed on the Group IV-based substrate, a GaN epitaxial layer formed on the AlN nucleation layer, a distributed Bragg reflector (DBR) multi-layer structure formed on the epitaxial layer, and an LED active layer formed on the DBR multi-layer structure.

Abstract: The invention provides a method for antivirus protection adapted for an electronic device. First, an option read only memory (ROM) is initialized. Second, all network connection ports of the electronic device are disabled. A first network connection port is enabled to connect the electronic device with an external system. Whether first antivirus software is installed on the electronic device is checked. If it is checked that the first antivirus software is not installed on the electronic device, after second antivirus software is received by the electronic device from the external system via the first network connection port and is installed on the electronic device, the electronic device enables all the network connection ports to connect the electronic device with the external system.

Abstract: GaN layer on semiconductor substrate is grown by using GaN nanorod buffer layer. Firstly, semiconductor substrate is cleaned and thermally degassed to remove the contaminant in the growth chamber. After the above step, the GaN nanorods layer is grown under the N-rich condition. Then, GaN epilayer is overgrown on the GaN nanorods layer under the Ga-rich condition for forming Group of III-Nitrides semiconductor layer on the semiconductor substrate.

Abstract: In the dual-band mixer of this invention, a current combined load is presented and is shared by two separate working frequency bands. In the invented dual-band mixer, a switch is provided to connect and disconnect an adjust capacitor series to the load inductors. By determining the capacitance of respective capacitors and the inductance of the load inductors, it is possible to generate resonance with related parasitic capacitances at particular frequencies, such that value of the load inductors may be changed. This enables the invented mixer to work with selected frequencies according to the operation of the switches. In addition, a systematic methodology is proposed to implement the design of the invented dual-band mixer. The efficient design method is approved by a 2.4/5.2-GHz CMOS mixer implementation.

Abstract: Disclosed are a backlight module and a liquid crystal display (LCD) including the same. The backlight module has a heat conductive structure so as to reduce the non-uniformity phenomenon of display. The backlight module comprises a frame, a reflective sheet, a heat-conductive plate, and a circuit board, wherein the frame has a bottom portion and at least one substantially step-typed through hole is formed therein. The reflective sheet is disposed on the inner surface of the bottom portion, and the heat-conductive plate is disposed in the step-typed through hole, and is spaced from the reflection sheet at a predetermined distance. The circuit board is disposed on the outer surface of the bottom portion of the frame, and has at least one electrical component that is received in the substantially step-typed through hole.

Abstract: The present invention discloses an architecture of a NMOS transistor with a compressive strained Si—Ge channel fabricated on a silicon (110) substrate, which comprises: a p-silicon (110) substrate, two n+ ion-implanted regions functioning as the source and the drain respectively, a compressive strained Si—Ge channel layer, and a gate structure. The compressive strained Si—Ge channel layer is grown on the p-silicon (110) substrate to reduce the electron conductivity effective mass in the [1_l -10] crystallographic direction and to promote the electron mobility in the [1-10] crystallographic direction. Thus, the present invention can improve the electron mobility of a NMOS transistor via the channels fabricated on the silicon (110) substrate. Further, the NMOS transistor of the present invention can combine with a high-speed PMOS transistor on a silicon (110) substrate to form a high-performance CMOS transistor on the same silicon (110) substrate.

Abstract: This invention provides a process for growing Ge epitaixial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaixial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaixial layer, such as Si0.1Ge0.9 in a thickness of 0.8 ?m on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si0.1Ge0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 ?m Si0.05Ge0.95 layer, and/or optionally a further 0.8 ?m Si0.02Ge0.98 layer, are grown.

Abstract: A flat display, a flat panel display and a backlight module are disclosed. The flat display module comprises the flat panel display and the backlight module. The flat panel display comprises an upper polarizer and a lower polarizer. The lower polarizer includes a first diffusion layer. The backlight module comprises a light emitting device, a prism sheet and a light guide plate. A light beam is provided by the light emitting device. The prism sheet is one-dimensional prism array structure. The light guide plate includes a second diffusion layer for diffusing the light beam. The first diffusion layer has an optical haze greater than the optical haze of the surface of the upper polarizer. Accordingly, thin thickness and high brightness are achieved for the flat display.

Abstract: In the dual-band mixer of this invention, a current combined load is presented and is shared by two separate working frequency bands. In the invented dual-band mixer, a switch is provided to connect and disconnect an adjust capacitor series to the load inductors. By determining the capacitance of respective capacitors and the inductance of the load inductors, it is possible to generate resonance with related parasitic capacitances at particular frequencies, such that value of the load inductors may be changed. This enables the invented mixer to work with selected frequencies according to the operation of the switches. In addition, a systematic methodology is proposed to implement the design of the invented dual-band mixer. The efficient design method is approved by a 2.4/5.2-GHz CMOS mixer implementation.

Abstract: A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1?x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1?x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.

Abstract: Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have different first and second dopant types, respectively. A semiconductor layer is formed over at least a portion of the second region. The metal layer is heated to form a metal gate electrode over the first region, and the metal layer and the semiconductor layer are collectively heated to form a composite metal gate electrode over the second region.

Abstract: This invention relates to an apparatus of catalytic molecule beam epitaxy (cat-MBE) and process for growing Group III nitride materials using thereof, characteristically in that said apparatus is equipped with a hot wire to catalytically decompose gaseous ammonium or nitrogen molecule into activated nitrogen radicals as the nitrogen source for growing epitaxial layers by MBE.

Abstract: Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have different first and second dopant types, respectively. A semiconductor layer is formed over at least a portion of the second region. The metal layer is heated to form a metal gate electrode over the first region, and the metal layer and the semiconductor layer are collectively heated to form a composite metal gate electrode over the second region.

Abstract: A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1-x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1-x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.

Abstract: A method of reducing the boron-penetrating of effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the silicon substrate in the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, boron ions (B+) are doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to form a polysilicon gate. The gate photoresist is used as a mask to dope boron difluoride ions (BF2+) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain region on the silicon substrate.

Abstract: A method for forming thin film transistor with lateral crystallization. The method at least includes the following steps. First of all, an insulation substrate is provided. Then, an amorphous silicon layer is provided on the insulation substrate. The seeds are formed by annealing a portion of said amorphous silicon layer by excimer laser system, and the lateral-growth grain is formed by using the seeds to grow laterally by annealing the amorphous silicon layer, wherein the amorphous silicon layer defines an active region. Then, sequentially a dielectric layer and a polysilicon layer is deposited on the active region, wherein the dielectric layer and the polysilicon layer are gate electrode, a gate is defined on the substrate, and the polysilicon layer is formed by etching. Next, source and drain regions are formed by implanting numerous ions into amorphous silicon layer by using the gate electrode as a mask.

Abstract: A method of forming a gate oxide layer with improved ability to resist process damage increases the reliability and yield of a transistor device. First, a nitrogen-containing gate oxide layer is formed on an element area of a silicon substrate. Then, a polysilicon layer is deposited on the gate oxide layer. Next, a gate doping process and a fluorine ion implantation are performed on the polysilicon layer. Then, a high-temperature tempering procedure is performed to make the fluorine enter the gate oxide layer.