Abstract: The present invention provides a semiconductor column structure which includes a light emitting layer and at least two facets with different crystalline orientations. The surface area ratio of the at least two facets is changed to alter the luminescence properties, such as CCT and CRI. Particularly, the surface area ratio of the at least two facets is adjusted in a range of from 1:0.1 to 1:10.

Abstract: A memory repairing method for a rewritable non-volatile memory module and a memory controller and a memory storage apparatus are provided. The method includes monitoring a wear degree of the rewritable non-volatile memory module; determining whether the wear degree of the rewritable non-volatile memory module is larger than a threshold; and heating the rewritable non-volatile memory module such that the temperature of the rewritable non-volatile memory module lies in between 100° C.˜600° C. if the wear degree of the rewritable non-volatile memory module is larger than the threshold. Accordingly, deteriorated memory cells in the rewritable non-volatile memory module can be repaired, thereby preventing data loss.

Abstract: A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and adjusting an initial write voltage and a write voltage pulse time corresponding to the memory cell based on the wear degree thereof. The method further includes programming the memory cell by applying the initial write voltage and the write voltage pulse time, thereby writing the data into the memory cell. Accordingly, data can be accurately stored into the rewritable non-volatile memory module by the method.

Abstract: A NAND flash memory includes a plurality of NAND flash memory structures separated by an insulating layer. In one embodiment of the present disclosure, the NAND flash memory structure includes a first bitline extending along a first direction, a first charge-trapping region positioned over the first bitline, a wordline positioned over the first charge-trapping region and extending along a second direction, a second charge-trapping region positioned over the wordline, and a second bitline positioned over the second charge-trapping region, wherein the first charge-trapping region and the second charge-trapping region are stacked along a third direction substantially perpendicular to the first direction and the second direction.

Abstract: The invention discloses an interactive simulated-globe display system including an imaging body, N image-projecting units, a data processing unit, an optical pointer, and M image-capturing units where N and M are respectively a natural number. The N image-projecting units project N images onto an external hemispheric surface of the imaging body. The N images constitute a hemi-globe image of a whole globe image. The data processing unit detects an indicated spot projected on the external hemispheric surface by the M image-capturing units, judges if a track relative to the indicated spot meets one of a plurality of position input rules, and if YES, executes an instruction corresponding to said one position input rule.

Abstract: A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and adjusting an initial write voltage and a write voltage pulse time corresponding to the memory cell based on the wear degree thereof. The method further includes programming the memory cell by applying the initial write voltage and the write voltage pulse time, thereby writing the data into the memory cell. Accordingly, data can be accurately stored into the rewritable non-volatile memory module by the method.

Abstract: A method of fabricating a light emitting device, comprising: providing a substrate; forming an undoped semiconductor layer on the substrate; forming a patterned metal layer on the undoped semiconductor layer; using the patterned metal layer as a mask to etch the undoped semiconductor layer and forming a plurality of nanorods on the substrate; and forming an light emitting stack on the plurality of nanorods to form a plurality of voids between the light emitting stack and the plurality of nanorods.

Abstract: A communication method of virtual machines and a server-end system are provided. A virtual hardware address is assigned to a virtual machine when the virtual machine are established, wherein the virtual hardware address includes a tenant identity. A validation procedure for a packet is performed when the virtual machine desires to communicate with another virtual machine by transmitting the packet, so as to determine whether the virtual hardware addresses of the source-end and the destination-end in the packet have the same tenant identity. If the both virtual hardware addresses have the same tenant identity, the packet is transmitted to the another virtual machine.

Abstract: A thin film solar cell with a graded bandgap structure comprises a front contact, a first light absorption layer, a transition layer, a second light absorption layer and a back contact. The first light absorption layer is formed on the front contact, the transition layer is formed on the first light absorption layer, the second light absorption layer is formed on the transition layer, and the back contact is formed on the second light absorption layer, wherein the transition layer has a graded bandgap, which is made by alternating a layer of the first superlattice layers, having a first bandgap, with a layer of the second superlattice layers, having a second bandgap, in a tandem arrangement, based on the condition that the thickness of each layer of the first and the second superlattice layers is varied increasing, decreasing or increasing first and then decreasing.

Abstract: A NAND flash memory includes a plurality of NAND flash memory structures separated by an insulating layer. In one embodiment of the present disclosure, the NAND flash memory structure includes a first bitline extending along a first direction, a first charge-trapping region positioned over the first bitline, a wordline positioned over the first charge-trapping region and extending along a second direction, a second charge-trapping region positioned over the wordline, and a second bitline positioned over the second charge-trapping region, wherein the first charge-trapping region and the second charge-trapping region are stacked along a third direction substantially perpendicular to the first direction and the second direction.

Abstract: A semiconductor structure includes a temporary substrate; a first semiconductor layer positioned on the temporary substrate; a dielectric layer comprising a plurality of patterned nano-scaled protrusions disposed on the first semiconductor layer; a dielectric layer surrounding the plurality of patterned nano-scaled protrusions and disposed on the first semiconductor layer; and a second semiconductor layer positioned on the dielectric layer, wherein the top surfaces of the patterned nano-scaled protrusions are in contact with the bottom of the second semiconductor layer. An etching process is performed on the semiconductor structure to separate the first semiconductor layer and the second semiconductor layer, in order to detach the temporary substrate from the second semiconductor layer and transfer the second semiconductor layer to a permanent substrate.

Abstract: An optical film assembly includes a first prism film and a first diffusing film. The first diffusing film is disposed on the first prism film. The first prism film has a plurality of prism structures arranged in parallel with each other and arranged in an orientation direction. The first diffusing film has a tensile direction. An angle included between the tensile direction of the first diffusing film and the orientation direction of the prism structures of the first prism film is between 50 degrees and 130 degrees.

Abstract: A magnetic capacitor includes two electrode layers, an insulator layer, and one or more magnetized layers. The insulator layer is located between the first electrode layer and the second electrode layer. The one or more magnetized layers include one or more ferro-magnetic elements that are magnetized. The one or more magnetized layers are located so that the one or more ferro-magnetic elements apply a magnetic field to the insulator layer to improve an electrical property of the insulator layer. Magnetic fields applied perpendicular to the electrode layers increase the capacitance and electrical energy storage of the insulator layer. Magnetic fields applied parallel to the electrode layers decrease the leakage current and increase the breakdown voltage of the insulator layer. The one or more ferro-magnetic elements used can include ferro-magnetic plates or magnetic nanodots. The one or more magnetized layers can be located between or outside of the electrode layers.

Abstract: The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element.

Abstract: A thin film solar cell with a graded bandgap structure comprises a front contact, a first light absorption layer, a transition layer, a second light absorption layer and a back contact. The first light absorption layer is formed on the front contact, the transition layer is formed on the first light absorption layer, the second light absorption layer is formed on the transition layer, and the back contact is formed on the second light absorption layer, wherein the transition layer has a graded bandgap, which is made by alternating a layer of the first superlattice layers, having a first bandgap, with a layer of the second superlattice layers, having a second bandgap, in a tandem arrangement, based on the condition that the thickness of each layer of the first and the second superlattice layers is varied increasing, decreasing or increasing first and then decreasing.

Abstract: The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element.

Abstract: A light emitting device (LED) structure formed on a Group IV-based semiconductor substrate is provided. The LED structure includes a Group IV-based substrate, an AlN nucleation layer formed on the Group IV-based substrate, a GaN epitaxial layer formed on the AlN nucleation layer, a distributed Bragg reflector (DBR) multi-layer structure formed on the epitaxial layer, and an LED active layer formed on the DBR multi-layer structure.

Abstract: The present invention provides a method for manufacturing a free-standing substrate, comprising: growing a first layer having a sacrificial layer on a growth substrate; patterning the first layer into a patterned first layer having a structure of a plurality of protrusions; growing a second layer on the patterned first layer having a structure of a plurality of protrusions by epitaxial lateral overgrowth; and separating the second layer from the growth substrate by etching away the sacrificial layer, wherein the separated second layer functions as a free-standing substrate for epitaxy.

Abstract: Heavily doped epitaxial SiGe material or epitaxial InxGa1-xAs are used to form the source and drain of III-V semiconductor device to apply stress to the channel of III-V semiconductor device. Therefore, the electron mobility can be increased.

Abstract: The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element.