Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Abstract: A light emitting device includes an epitaxial structure and first and second electrodes on a side of the epitaxial structure. The epitaxial structure includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode is disposed on the epitaxial structure to be electrically connected with the first-type semiconductor layer. The second electrode is disposed on the epitaxial structure to be electrically connected with the second-type semiconductor layer. The second electrode is in ohmic contact with a second-type window sublayer of the second-type semiconductor layer.

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Abstract: A method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ILD) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ILD layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to NH-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to N-terminated, while leaving the surfaces of the bottom portion of the trench being NH-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.

Abstract: An optical film, an optical film set, a backlight module and a display device are provided. The optical film includes a main body, plural first prism structures and plural second prism structures. The main body has a first optical surface and a second optical surface. The first prism structures are disposed on the first optical surface. Each of the first prism structures extends along a first direction. The second prism structures are disposed on the second optical surface. Each of the second prism structures extends along a second direction. The first direction is different from the second direction.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A PVC resin composition and a method for manufacturing a pipe having high heat resistance and transparency are provided. The PVC resin composition includes 100 phr of a PVC resin, 0.5 phr to 5 phr of a modifier, and 1 phr to 10 phr of a heat resistance improving agent. A degree of polymerization of the PVC resin is from 800 to 1,350. The modifier is a polymer containing a first monomer and a second monomer. The first monomer is ethylene or a derivative of the ethylene, and the second monomer is a polyester.

Abstract: A composition and a manufacturing method of a highly flame-retardant and low-smoke injection-molded polyvinyl chloride pipe are provided. The composition includes a polyvinyl chloride resin material, a chlorinated polyvinyl chloride resin material, a flame retardant additive and a carbon forming additive. A first number-average degree of polymerization (DPn) of the polyvinyl chloride resin material is between 600 and 1,000. A second number-average degree of polymerization of the chlorinated polyvinyl chloride resin material is between 600 and 800. A difference between the first number-average degree of polymerization and the second number-average degree of polymerization is within 400. The flame retardant additive is a phosphorus-containing flame retardant modified by a modifier. A total added amount of the flame retardant additive and the carbon forming additive in the composition is not greater than 3 PHR.

Abstract: A composition and a manufacturing method of a highly flame-retardant and low-smoke extruded polyvinyl chloride pipe are provided. The composition includes a polyvinyl chloride resin material, a flame retardant additive and a carbon forming additive. The polyvinyl chloride resin material is in an amount between 10 PHR (parts per hundred resin) and 90 PHR. The flame retardant additive is in an amount between 0.5 PHR and 2.0 PHR, and is a phosphorus-containing flame retardant modified by a modifier. The carbon forming additive is in an amount between 0.2 PHR and 1.0 PHR. The carbon forming additive is at least one material selected from a group consisting of zinc chloride, zinc stearate, calcium stearate, zinc hydroxystannate, anhydrous zinc stannate, zinc phosphate and zirconium phosphate. A total added amount of the flame retardant additive and the carbon forming additive in the composition is not greater than 3 PHR.

Abstract: A chlorinated polyvinyl chloride resin composition, an extruded sheet and a method for manufacturing the same are provided. The chlorinated polyvinyl chloride resin composition includes a chlorinated polyvinyl chloride resin and a plasticizing processing aid. The chlorinated polyvinyl chloride resin has an amount of 80 parts by weight to 120 parts by weight, a degree of polymerization of from 500 to 1,100, and a chlorine content of from 60% to 75%. The plasticizing processing aid includes a vinyl chloride graft copolymer and an acrylic compound. A grafted functional group of the vinyl chloride graft copolymer is at least one of polyol ester and ethylene vinyl acetate.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.

Abstract: A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The i magnetic element is wider than the isolation element. The semiconductor device structure further includes a conductive line over the isolation element.

Abstract: A semiconductor light-emitting device includes a bonding substrate, a multi-layered metal unit, and a semiconductor lighting unit. The bonding substrate includes an upper surface and a lower surface opposite to the upper surface. The multi-layered metal unit is disposed on the upper surface of the bonding substrate such that an exposed region of the upper surface of the bonding substrate is exposed from the multi-layered metal unit. The semiconductor lighting unit is disposed on the multi-layered metal unit opposite to the bonding substrate. A method for manufacturing the semiconductor light-emitting device is also disclosed.

Abstract: An optical film comprises a light incident side and a light emitting side opposite to the light incident side. A plurality of light incident microstructures are formed on the light incident side, and the light incident microstructures are tapered structures. According to the structural design of the light incident microstructures of the optical film, the light field of a light source can be expanded to achieve the purpose of emitting light at a specific angle. The invention also provides a backlight module and a display device including the optical film.

Abstract: A flip-chip light emitting diode includes a light-emitting epitaxial laminated layer having a first surface, and a second surface opposing the first surface, and including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein the first surface is a roughened surface; a transparent bonding medium layer over the first surface of the light-emitting epitaxial laminated layer and bonded with a transparent substrate; and a first electrode and a second electrode respectively over a first electrode region and a second electrode region over the second surface of the light-emitting epitaxial laminated layer.