Patents by Inventor Chun-Yi Wu

Chun-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230092504
    Abstract: A light-emitting diode includes a light-emitting epitaxial layer having a first surface as a light-emitting surface and a second surface opposing the first surface, a first type semiconductor layer, an active layer, and a second type semiconductor layer; a transparent dielectric layer located on the second surface and in direct contact with the light-emitting epitaxial laminated layer, and having conductive through-holes therein; a transparent conductive layer located on one side surface of the transparent dielectric layer that is distal from the light-emitting epitaxial laminated layer; and a metal reflective layer located on one side surface of the transparent conductive layer that is distal from the transparent dielectric layer; wherein the transparent dielectric layer includes a first layer and a second layer; and wherein the first layer is thicker than the second layer, and a refractivity of the first layer is less than a refractivity of the second layer.
    Type: Application
    Filed: October 31, 2022
    Publication date: March 23, 2023
    Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Cheng MENG, Yuehua JIA, Jing WANG, Chun-Yi WU, Ching-Shan TAO, Duxiang WANG
  • Patent number: 11588036
    Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 21, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei Yu, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
  • Publication number: 20230050100
    Abstract: An optical film includes a substrate layer and a plurality of optical layers stacked on the substrate layer. The at least two optical layers have microstructures that complement to each other. The optical layer close to the substrate layer is the first optical layer, and the optical far from the substrate layer is the second optical layer. The refractive index of the first optical layer is smaller than the second optical layer, and the microstructure of the second optical layer has an acute angle. Because of the arrangement of the optical layers, the contrast of light intensity can be reduced, and the uniformity can be improved. The invention also provides a backlight module and a display device including the optical film.
    Type: Application
    Filed: May 4, 2022
    Publication date: February 16, 2023
    Applicant: Radiant Opto-Electronics Corporation
    Inventors: Chun-Hau LAI, Wei-Hsuan CHEN, Yung-Hui TAI, Chun-Yi WU, Yuan-Chen CHUNG
  • Patent number: 11563140
    Abstract: A method for producing a light omitting device includes providing a substrate and forming an epitaxial structure thereon, forming first and second electrodes on a side of the epitaxial structure facing away from the substrate, and removing the substrate. The epitaxial structure includes a first-type semiconductor layer, an active layer, a second-type semiconductor layer, and an AlGaAs-based semiconductor layer formed on the substrate in a distal-to-proximal manner. The AlGaAs-based semiconductor layer has a thickness of not less than 30 ?m, and is configured to support the rest of the epitaxial structure and serve as a light exiting layer. The device produced by the method is also disclosed.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: January 24, 2023
    Assignee: Tiajin Sanan Optoelectornics Co., Ltd.
    Inventors: ChingYuan Tsai, Chun-Yi Wu, Fulong Li, Duxiang Wang, Chaoyu Wu, Wenhao Gao, Xiaofeng LiU, Weihuan Li, Liming Shu, Chao Liu
  • Publication number: 20230013893
    Abstract: A backlight module includes at least one optical film and a backlight unit. The optical film has a light incident side and a light emitting side opposite to the light incident side. A plurality of light incident microstructures are formed on the light incident side, and the light incident microstructures are tapered structures. The backlight unit is disposed on the light incident side of the optical film and includes a light source. According to the structural design of the light incident microstructures of the optical film, the light field of the light source can be expanded to achieve the purpose of emitting light at a specific angle. The invention also provides a display device including the backlight module.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 19, 2023
    Applicant: Radiant Opto-Electronics Corporation
    Inventors: Wei-Hsuan CHEN, Chung-Yung TAI, Wen-Hao CAI, Chun-Yi WU
  • Patent number: 11522107
    Abstract: A light-emitting diode includes a light-emitting epitaxial layer having a first surface as a light-emitting surface and a second, opposing, surface, including a first type semiconductor layer, an active layer, and a second type semiconductor layer; a metal reflective layer disposed over the second surface; and a protective layer formed seamlessly on a surface of the metal reflective layer and on a side wall of the metal reflective layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: December 6, 2022
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Cheng Meng, Yuehua Jia, Jing Wang, Chun-Yi Wu, Ching-Shan Tao, Duxiang Wang
  • Publication number: 20220384688
    Abstract: A micro light-emitting diode (LED) includes an epitaxial layered structure including a support layer, a first-type semiconductor element, an active layer, and a second-type semiconductor element that are sequentially disposed on one another in such order. The micro LED is substrate-free, and the support layer has a thickness equal to or greater than 500 nm. A micro LED array is also disclosed.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Cuicui SHENG, Chun-Kai HUANG, Chun-Yi WU
  • Publication number: 20220262892
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The i magnetic element is wider than the isolation element. The semiconductor device structure further includes a conductive line over the isolation element.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Yu KU, Chi-Cheng CHEN, Hon-Lin HUANG, Wei-Li HUANG, Chun-Yi WU, Chen-Shien CHEN
  • Patent number: 11417801
    Abstract: A micro light-emitting diode (LED) includes an epitaxial layered structure including a support layer, a first-type semiconductor element, an active layer, and a second-type semiconductor element that are sequentially disposed on one another in such order. A method for manufacturing a micro LED device including at least one of the micro LED is also disclosed.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 16, 2022
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Cuicui Sheng, Chun Kai Huang, Chun-Yi Wu
  • Patent number: 11398546
    Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: July 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chun-Yi Wu, Chih-Yen Chen, Chang-Xiang Hung, Chia-Ching Huang
  • Publication number: 20220199438
    Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
  • Publication number: 20220149170
    Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Inventors: Hsiu-Mei Yu, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
  • Patent number: 11329124
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The isolation element partially covers a top surface of the magnetic element. The semiconductor device structure further includes a conductive line over the isolation element. In addition, the semiconductor device structure includes a dielectric layer over the conductive line and the magnetic element.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Patent number: 11309201
    Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 19, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu
  • Patent number: 11289407
    Abstract: A package structure is provided. The package structure includes a die, a lead frame, and a conductive glue. The lead frame includes a die pad and a retaining wall structure. The die pad is configured to support the die, and the retaining wall structure surrounds the die. The conductive glue is disposed between the die and the lead frame.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: March 29, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Chun-Yi Wu
  • Publication number: 20220077370
    Abstract: A light-emitting component includes a light-emitting unit and an electrically insulating layer. The light-emitting unit includes a first semiconductor layer, an active layer, and a second semiconductor layer, which are stacked on one another along a stacking direction in such order. The second semiconductor has a lower surface distal from the active layer. The electrically insulating layer is disposed to cover a first portion and to expose a second portion of the lower surface of the second semiconductor layer. A fluorine-containing region is formed in the second semiconductor layer. Methods for making the light-emitting component are also disclosed.
    Type: Application
    Filed: November 15, 2021
    Publication date: March 10, 2022
    Inventors: Dongyan ZHANG, Yuehua JIA, Chun-Yi WU, Wen LIU, Jing WANG, Huan-Shao KUO, Huiwen LI, Duxiang WANG
  • Publication number: 20210398883
    Abstract: A package structure is provided. The package structure includes a die, a lead frame, and a conductive glue. The lead frame includes a die pad and a retaining wall structure. The die pad is configured to support the die, and the retaining wall structure surrounds the die. The conductive glue is disposed between the die and the lead frame.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen CHEN, Chun-Yi WU
  • Patent number: 11201234
    Abstract: A high-electron mobility transistor (HEMT) includes a substrate, a group III-V channel layer, a group III-V barrier layer, a group III-V cap layer, a source electrode, a first drain electrode, a second drain electrode, and a connecting portion. The group III-V channel layer, the group III-V barrier layer, and the group III-V cap layer are sequentially disposed on the substrate. The source electrode is disposed at one side of the group III-V cap layer, and the first and second drain electrodes are disposed at another side of the group III-V cap layer. The bottom surface of the first drain electrode is separated from the bottom surface of the second drain electrode, and the composition of the first drain electrode is different from the composition of the second drain electrode. The connecting portion is electrically coupled to the first drain electrode and the second drain electrode.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 14, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Ching Huang, Chih-Yen Chen, Chun-Yi Wu, Chih-Jen Hsiao
  • Publication number: 20210376054
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation layer covering the magnetic element and a portion of the semiconductor substrate. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding edges of the magnetic element.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chun-Yi WU, Kuang-Yi WU, Hon-Lin HUANG, Chih-Hung SU, Chin-Yu KU, Chen-Shien CHEN
  • Publication number: 20210358786
    Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Inventors: Hsiu-Mei Yu, Wei-Chan Chang, Chang-Sheng Lin, Chun-Yi Wu