Abstract: The present disclosure discloses tribenzotriquinacene with an axial aryl group and a method for preparing the same. The triphenyltripentacene has a structure shown in formula (1): R1 and R2 are independently hydrogen, a C1-C12 alkyl group, a C1-C12 alkoxy group, a C1-C12 fluoroalkyl group, a C1-C12 fluorine-containing alkoxy group, a C1-C12 ester group, a halogen group, a nitro group, an amine group, a cyano group, or a hydroxy group.

Abstract: A method for analyzing aortic CT images includes: receiving multiple original CT images and selecting a sequence of chest CT images therefrom; generating, using a part detection model, for each of the chest CT images, a detection result that indicates whether the chest CT image represents an ascending aorta; generating, using a status analysis model, for each of the chest CT images, an analysis result that indicates whether the chest CT image shows aortic dissection; and when determining that at least N chest CT image(s) from consecutive M number of the chest CT images show aortic dissection, determining whether the detection result of at least one of the at least N chest CT image(s) represents an ascending aorta, and if affirmative, generating a type A aortic dissection result or otherwise, generating a type B aortic dissection result.

Abstract: A method includes forming a device layer on a first surface of a first substrate, forming a first interconnect structure over the device layer, depositing a bonding layer over the first interconnect structure, forming a diamond layer over the bonding layer, performing a laser treatment on a top portion of the diamond layer by applying laser energy to the top portion of the diamond layer using a laser beam, and performing a thinning process on the diamond layer to remove the top portion of the diamond layer.

Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a plurality of workloads for graphics processing. The apparatus may also perform a binning process for a first workload of the plurality of workloads. Further, the apparatus may divide the first workload into a plurality of first sub-workloads and a second workload of the plurality of workloads into a plurality of second sub-workloads. The apparatus may also perform a rendering process for at least one first sub-workload of the plurality of first sub-workloads and a binning process for at least one second sub-workload of the plurality of second sub-workloads. The apparatus may also perform a rendering process for the at least one second sub-workload prior to a completion of the rendering process for the at least one first sub-workload.

Abstract: A method includes performing a cleaning process on a first surface of a first wafer, and performing a surface activation process on the first surface. The surface activation process is selected from the group consisting of: a plasma surface activation process comprising generating a plasma from a process gas, wherein ions in the plasma are removed using a filter, and wherein a remaining uncharged part of the plasma is used to treat the first surface; a laser surface activation process using a laser beam; an acid surface activation process using an acid; and an alkali surface activation process using an alkali. After the surface activation process, a rinsing process is performed on the first surface. The first surface of the first wafer is bonded to a second surface of a second wafer.

Abstract: A method includes forming a lower semiconductor region, forming an upper semiconductor region overlapping the lower semiconductor region, forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively, forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric, etching back the lower gate electrode, forming a gate isolation layer on the lower gate electrode that has been etched back, and forming an upper gate electrode over the gate isolation layer. The upper gate electrode is on the upper gate dielectric.

Abstract: A semiconductor device includes a semiconductor stack, a third semiconductor structure, a dielectric layer, and a reflective layer under the third semiconductor structure. The semiconductor stack includes a first semiconductor structure, an active structure, a second semiconductor structure. The first semiconductor structure has a first surface which includes a first portion and a second portion, and the first surface has a first area. The third semiconductor structure connects to the first portion, and has a second surface with a second area. The dielectric layer connects to the second portion and includes a plurality of openings, and the plurality of openings have a third area. A ratio of the second area to the first area is between 0.1˜0.7, and a ratio of the third area to the first area is less than 0.2.

Abstract: The present disclosure describes novel compounds, or their pharmaceutically acceptable salts, pharmaceutical compositions containing them, and their medical uses. Compounds of the disclosure have activity as dual modulators of Janus kinase (JAK), alone, or in combination with one or more of an additional mechanism, including a tyrosine kinase, such as TrkA or Syk, and PDE4, and are useful in the in the treatment or control of inflammation, auto-immune diseases, cancer, and other disorders and indications where modulation of JAK would be desirable. Also described herein are methods of treating inflammation, auto-immune diseases, cancer, and other conditions susceptible to inhibition of JAK and PDE4 by administering a compound herein described.

Abstract: The present invention relates to a secondary battery module, a secondary battery pack including the same, and a secondary battery module inspection device for inspecting the secondary battery module, and more particularly, to a secondary battery module including a plurality of secondary batteries, a secondary battery pack including the same, and a secondary battery module inspection device for inspecting the secondary battery module. The present invention provides a secondary battery module including: a plurality of secondary batteries arranged in parallel to each other; and a plurality of buffer pads inserted to be adjacent to the secondary batteries along an arrangement direction of the plurality of secondary batteries, wherein the plurality of buffer pads are provided to have thicknesses different from each other and are selectively inserted according to thicknesses of the adjacent secondary batteries.

Abstract: High resolution 3D thermal imaging can be obtained by using enhanced non-destructive heat transducer designs. A thermal property measurement method includes providing a sample for thermal property measurement, and bonding a transducer layer on the sample through a temporary bonding layer. Thermal measurement processes are performed along the X-Y, X-Z and Y-Z planes of the sample, wherein the X-Y plane is parallel to a top surface of the sample, and the X-Z plane and Y-Z plane are perpendicular to the top surface of the sample. Each thermal measurement processes include heating a designated region of the sample covered with the transducer layer using a pump laser, and using a probe laser for generating a reflectance signal of the sample, and determining a thermal conductivity in the designated region of the sample from the reflectance signal. Furthermore, the transducer layer is removed along with the temporary bonding layer from the sample.

Abstract: A display system and a display method are provided. The display system comprises: a stylus, a touchscreen display, and a terminal device. The touchscreen display comprises a frame and a sensor. The sensor detects whether the stylus is near the frame. The terminal device communicatively connects to the touchscreen display. In response to the stylus being moved away from the frame, the touchscreen display transmits an operation signal to the terminal device and controls the terminal device according to the operation signal.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a device region, an inner ring surrounding the device region, an outer ring surrounding the inner ring, a first corner area between an outer corner of the inner ring and an inner corner of the outer ring, and a second corner area disposed at an outer corner of the outer ring. The first corner area includes a first active region including a channel region and a source/drain region, a first gate structure over the channel region of the first active region, and a first source/drain contact over the source/drain region of the first active region. The first source/drain contact continuously extends from a first edge of the first corner area to a second edge of the first corner area.

Abstract: Embodiments of the present disclosure relates to a wet bench processing including an in-situ pre-treatment prior to performing the first set of wet bench operations. The pre-treatment may include a pre-clean operation and/or a pre-heat operation. The pre-treatment may be performed in one of the existing ONB tanks without requiring adding new tanks to an existing wet bench tool. The pre-clean operation removes particles from a batch of wafers to avoid or reduce cross-contamination and defect issues, thus improving the yield rate of the wet bench process. The pre-heat operation provides better control and stabilize the temperature in the CHB tank to stabilize the process, such as to stabilize an etch rate.

Abstract: Integrated circuit (IC) chips are provided. An IC chip according to the present corner area between an outer corner of the device region and an inner corner of the ring region. The ring region includes a first active region extending along a first direction, a first source/drain contact disposed partially over the first active region and extending along the first direction, and first gate structures disposed completely over the first active region and each extending lengthwise along the first direction. The corner area includes a second active region extending along a second direction that forms an acute angle with the first direction, a second source/drain contact disposed partially over the second active region and extending along the second direction, and second gate structures disposed over the second active region and each extending along the first direction.

Abstract: A semiconductor structure includes a substrate, a circuit region, and a seal ring surrounding the circuit region. The circuit region includes two first source/drains, first semiconductor layers connecting the two first source/drains, and a first gate disposed between the two first source/drains and wrapping around each of the first semiconductor layers. The seal ring includes two epitaxially grown semiconductor structures, second semiconductor layers, third semiconductor layers, and a second gate. The second and the third semiconductor layers are alternately stacked one over another to form a stack of layers. A topmost layer of the stack is one of the third semiconductor layers. The second gate is disposed between the two epitaxially grown semiconductor structures and above the topmost layer of the stack. The first and the third semiconductor layers include a first semiconductor material. The second semiconductor layers include a second semiconductor material different from the first semiconductor material.

Abstract: A magnetic component is provided. The cross-sectional area of each lateral core part of the magnetic component is less than or equal to the cross-sectional area of the first middle core part. The magnetic component generates nonlinear inductance variations at different currents for achieving different coupling coefficients. Consequently, when the magnetic component operates at low current, the magnetic component maintains a non-coupled high inductance. On the other hand, when the magnetic component operates at high current, the magnetic component achieves high saturation and reduced inductance by the lateral core parts of the magnetic component. Simultaneously, the coupling degree is increased automatically, the AC current peak is reduced, and the magnetic flux is evenly distributed on the upper cover core part or the lower cover core part. Consequently, the magnetic component has advantage of reducing the component loss and the conduction loss in the power supply.

Abstract: A driving method includes the following steps. An input image is divided into a plurality of image blocks. A plurality of pixel groups corresponding to the image blocks are respectively controlled. Step of controlling a corresponding one of the pixel groups corresponding to one of the image blocks includes the following steps. A plurality of input grayscale values included in one of the image blocks are mapped to a plurality of duty cycles. One of the duty cycles is determined as a desired duty cycle. A plurality of the input grayscale values are mapped to a plurality of data voltages according to the desired duty cycle. A plurality of pixel circuits included in the one of the pixel groups are driven according to the desired duty cycle and the data voltages.

Abstract: A backlight control circuit includes LED circuits, a LED driver circuit, first switches and a switch module circuit. Each LED circuit includes a first and a second terminal. The second terminals of the LED circuits are connected. The LED driver circuit provides driving signals and dimming signal in sequence and provides error detection signals when the LED circuit is shorted or opened. The first switches are connected to the first terminals of the LED circuits for switching on or off the LED circuits based on the error detection signals. The switch module circuit includes second switches and third switches for timing provision of dimming signal. When a short or open circuit occurs, the error detection signal turns off corresponding first switch and third switch, so that the first terminal of the shorted/opened LED circuit is floating, and the second terminals can receive the dimming signal in other timing periods.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a base structure with first and second base portions disposed on the substrate, an isolation region disposed on the substrate and adjacent to the base structure, a nanostructured channel region disposed on the first base portion, a source/drain region disposed on the second base portion, a gate structure, and a gate spacer disposed along sidewalls of the gate structure and between the gate structure and the isolation region. The gate structure includes an outer gate portion comprising a tapered cross-sectional profile and disposed on the isolation region and an inner gate portion including a non-tapered cross-sectional profile and disposed on the nanostructured channel region.

Abstract: The present invention provides a nucleic acid extraction instrument including a base, an outer housing connected with the base, and an instrumental main body positioned inside the outer housing and mounted to the base; and the instrumental main body includes an electrical power pack, a main control device, a first motor set, a second motor set, and a third motor set.