Patents by Inventor Chun Yu

Chun Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250051441
    Abstract: This disclosure relates to protein complexes targeting CD47 and 4-1BB, and methods of use thereof. In one aspect, the protein complexes include one or more CD47-binding domains including all or a portion of the SIRP? extracellular regions, and one or more 4-1BB-binding domains including all or a portion of the 4-1BBL extracellular region.
    Type: Application
    Filed: December 9, 2022
    Publication date: February 13, 2025
    Inventors: Chun-Yu Lin, Shih-Han Huang, Yi-Chun HSIEH, Chi-Ling Tseng
  • Patent number: 12221411
    Abstract: The invention relates to processes for preparing carbaprostacyclin analogues and intermediates prepared from the processes. The invention also relates to cyclopentenone intermediates in racemic or optically active form.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: February 11, 2025
    Assignee: CHIROGATE INTERNATIONAL INC.
    Inventors: Chun-Yu Lin, Tzyh-Mann Wei, Shih-Yi Wei
  • Patent number: 12214462
    Abstract: A monitoring method and a monitoring system for a machine tool to machine a workpiece are provided. The monitoring method includes the following steps. First, a vibration signal of a spindle of the machine tool is detected. Next, a vibration feature value of the vibration signal is obtained. Whether the vibration feature value exceeds a threshold condition is determined, wherein the threshold condition is determined by a training model based on a predetermined surface quality of the workpiece. When the vibration feature value exceeds the threshold condition, a machining parameter of the machine tool is adjusted.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: February 4, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Yu Tsai, Chi-Chen Lin, Sheng-Ming Ma, Ta-Jen Peng
  • Patent number: 12211917
    Abstract: A method includes providing a structure having a substrate and first and second semiconductor layers alternately stacked one over another above the substrate, etching the first and the second semiconductor layers to form a first continuous ring in a seal ring region of the structure, and forming an isolation structure adjacent the first continuous ring in the seal ring region. The method further includes forming a dummy gate structure that is disposed directly above the first continuous ring and completely within a boundary of the first continuous ring from a top view, growing first and second epitaxial features sandwiching the dummy gate structure, removing the dummy gate structure, resulting in a gate trench that exposes a topmost layer of the first semiconductor layers and does not expose side surfaces of the first and second semiconductor layers, and depositing a gate structure in the gate trench.
    Type: Grant
    Filed: June 5, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Yu Chen, Yen Lian Lai
  • Patent number: 12190653
    Abstract: Disclosed are systems and methods to detect and identify vehicular anomalies. Techniques to detect and identify the vehicular anomalies include receiving signals from various sensors, grouping the signals into detection sets, detecting anomalies by a comparison to vehicle behavior models, and cross-referencing the detection sets with each other to narrow down and identify the source of the anomaly. The detection sets may be grouped such that facets of vehicle maneuverability are captured and cover causal relations between different maneuverability mechanisms.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: January 7, 2025
    Assignees: Ford Global Technologies, LLC, Regents of the University of Michigan
    Inventors: Yu Seung Kim, Chun-Yu Chen, Kang Shin
  • Patent number: 12181727
    Abstract: The present invention provides a lens assembly and a mobile terminal. The lens assembly includes a lens and a protective casing. The lens and the protective casing are fixedly connected to the mobile terminal separately. The lens is sheathed in the protective casing. A spacing exists between the protective casing and the lens. In the lens assembly and the mobile terminal provided in this embodiment, when the lens assembly is impacted, the protective casing receives the impact first and is deformed. Without direct connection or contact between the lens and the protective casing, a force received by the protective casing will not be directly transmitted to the lens, and the lens will not be pressed to deform by the protective casing, thereby avoiding a circumstance in which the deformation of the lens makes the mobile terminal unable to accurately recognize an obstacle.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: December 31, 2024
    Assignee: AUTEL ROBOTICS CO., LTD.
    Inventors: Chun Yu, Wenchao Zhang
  • Patent number: 12182657
    Abstract: A barcode image recognition method includes the following steps: capturing at least one barcode to generate a preview image, the preview image having at least one barcode image of the at least one barcode; decoding the barcode image to obtain barcode information and a plurality of vertex coordinates of the barcode image; caching the barcode information of the barcode image; forming a plurality of image boundaries of the barcode image with the plurality of vertex coordinates of the barcode image; generating a detection beeline from a specified point to a side edge of the preview image; determining the number of intersections of the plurality of image boundaries of the barcode image and the detection beeline; identifying the barcode image with odd number of intersections from the at least one barcode image as a target image; and outputting the barcode information of the target image.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: December 31, 2024
    Assignee: Getac Technology Corporation
    Inventors: Chun-Yu Kuo, Da-Ke Liu
  • Publication number: 20240421253
    Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure located on the substrate, a second type semiconductor structure located on the first type semiconductor structure, an active structure located between the first type semiconductor structure and the second type semiconductor structure, a plurality of contact portions disposed between the first type semiconductor structure and the substrate, and a first conductive oxide layer, a second conductive oxide layer, a first insulating layer and a second insulating layer. The plurality of contact portions is separated from each other, and one of them includes a semiconductor and has a side wall. The first conductive oxide layer contacts the contact portion, and the second conductive oxide layer contacts the first conductive oxide layer. The first insulating layer contacts the side wall. The second insulating layer is disposed between the first insulating layer and the second conductive oxide layer.
    Type: Application
    Filed: August 26, 2024
    Publication date: December 19, 2024
    Inventors: Chung-Hao WANG, Yu-Chi WANG, Yi-Ming CHEN, Yi-Yang CHIU, Chun-Yu LIN
  • Patent number: 12170235
    Abstract: A semiconductor structure according to the present disclosure includes a circuit region disposed over a substrate and a seal ring region disposed over the substrate and completely surrounding the circuit region. The circuit region includes first fins, second fins, n-type epitaxial structures over the first fins, and p-type epitaxial structures over the second fins. The seal ring region includes fin rings extending completely around the circuit region, epitaxial rings disposed over and extending parallel to the fin rings. All of the epitaxial rings over all of the fin rings in the seal ring region are p-type epitaxial rings.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Yu Chen, Yen Lian Lai
  • Publication number: 20240413268
    Abstract: A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.
    Type: Application
    Filed: June 7, 2024
    Publication date: December 12, 2024
    Inventors: Yi-Yang CHIU, Chun-Yu LIN, Chun Wei CHANG, Yi-Ming CHEN, Chen OU, Hung-Yu CHOU, Liang-Yi WU, Hsiao-Chi YANG
  • Patent number: 12166278
    Abstract: A transparent antenna includes a substrate, an antenna grid layer, and a ground grid layer. The substrate has an electrically conductive hole extending from two opposite surfaced of the substrate. The antenna grid layer is formed on a surface of the substrate. The antenna grid layer includes a feeding portion and a transmission portion. The ground grid layer is formed on another surface of the substrate. The ground grid layer is coupled to the feeding portion of the antenna grid layer via the electrically conductive hole. An offset distance between a projection of a gridline of the antenna grid layer on the first surface and a projection of a gridline of the ground grid layer on the first surface is smaller than or equal to half of a difference between a line width of the antenna grid layer and a line width of the ground grid layer.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: December 10, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Ming Lin, Wei Chung, Chen-Chun Yu, Hsin-Chu Chen, Wei-Yu Li
  • Patent number: 12154591
    Abstract: An electronic device configured with a microphone, a voice interaction wake-up method executed by an electronic device equipped with a microphone, and a computer-readable medium, the electronic device comprising a memory and a central processing unit, wherein the memory stores computer-executable instructions, and when executed by the central processing unit, the computer-executable instructions perform the following operations: analyzing a sound signal collected by a microphone, identifying whether the sound signal contains speech spoken by a person and whether it contains wind noise sounds generated by airflows hitting the microphone as a result of the speech spoken by the person, and in response to determining that the sound signal contains sound spoken by the person and contains wind noise sounds generated by airflows hitting the microphone as a result of the speech spoken by the user, processing the sound signal as speech input by the user.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 26, 2024
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Chun Yu, Yuanchun Shi
  • Publication number: 20240387692
    Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yu KUO, Shang-Yun HUANG, Chin-Yin KUO
  • Patent number: 12147334
    Abstract: The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: November 19, 2024
    Assignee: SILICON MOTION, INC.
    Inventor: Chun-Yu Chen
  • Publication number: 20240379359
    Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Chun-Yu Kao, Sung-En Lin, Chia-Cheng Chao
  • Publication number: 20240379587
    Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes an interconnect structure that includes a first metal line, a second metal line, a third metal line, a fourth metal line, and a fifth meal line extending along a first direction, a first group of lateral connectors disposed between the second metal line and the third metal line or between the fourth metal line and the fifth metal line, and a second group of lateral connectors disposed between the first metal line and the second metal line or between the third metal line and the fourth metal line.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Yen Lian LAI, Chun Yu CHEN
  • Patent number: 12142666
    Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Yu Kuo, Shang-Yun Huang, Chih-Yin Kuo
  • Publication number: 20240368196
    Abstract: The present disclosure describes novel compounds, or their pharmaceutically acceptable salts, pharmaceutical compositions containing them, and their medical uses. Compounds of the disclosure have activity as dual modulators of Janus kinase (JAK), alone, or in combination with one or more of an additional mechanism, including a tyrosine kinase, such as TrkA or Syk, and PDE4, and are useful in the in the treatment or control of inflammation, auto-immune diseases, cancer, and other disorders and indications where modulation of JAK would be desirable. Also described herein are methods of treating inflammation, auto-immune diseases, cancer, and other conditions susceptible to inhibition of JAK and PDE4 by administering a compound herein described.
    Type: Application
    Filed: July 2, 2020
    Publication date: November 7, 2024
    Inventors: Yasheen ZHOU, Chun Yu LIU, Chunliang LIU, Yong-Kang ZHANG
  • Publication number: 20240373187
    Abstract: An audio parameter optimizing method and a computing apparatus related to audio parameters. In the method, sound features of multiple sound signals are obtained. A wide dynamic range compression (WDRC) parameter corresponding to each of the sound signals is determined. Multiple data sets including the sound features and the corresponding WDRC parameters of the sound signals are created. The data sets are used to train a neural network, so as to generate a parameter inference model. The parameter inference model is configured to determine the WDRC parameter of a to-be-evaluated signal. Accordingly, a proper parameter could be provided.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 7, 2024
    Applicant: Acer Incorporated
    Inventors: Po-Jen Tu, Kai-Meng Tzeng, Jia-Ren Chang, Chien-Chung Chen, Ming-Chun Yu, Feng-Ming Liu, Hung-Lun Lu
  • Patent number: 12136379
    Abstract: A display panel includes a plurality of driving electrode regions and a plurality of wiring regions connected between the driving electrode regions. A (2n?1)th wiring region extended from a (2n?1)th driving electrode region toward a (2n)th driving electrode region has a wiring extending direction forming a first included angle with an arrangement direction, and a (2n)th wiring region extended from the (2n)th driving electrode region toward a (2n+1)th driving electrode region has a wiring extending direction forming a second included angle with the arrangement direction, and a (2n+1)th wiring region extended from the (2n+1)th driving electrode region toward a (2n+2)th driving electrode region has a wiring extending direction forming a third included angle with the arrangement direction, wherein n is a positive integer. At least one of the first included angle, the second included angle and the third included angle is positive and at least one of them is negative.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: November 5, 2024
    Assignee: AUO Corporation
    Inventors: Chun-Yu Lin, Kun-Cheng Tien, Jia-Long Wu, Rong-Fu Lin, Shu-Hao Huang