Abstract: The present invention provides a lens assembly and a mobile terminal. The lens assembly includes a lens and a protective casing. The lens and the protective casing are fixedly connected to the mobile terminal separately. The lens is sheathed in the protective casing. A spacing exists between the protective casing and the lens. In the lens assembly and the mobile terminal provided in this embodiment, when the lens assembly is impacted, the protective casing receives the impact first and is deformed. Without direct connection or contact between the lens and the protective casing, a force received by the protective casing will not be directly transmitted to the lens, and the lens will not be pressed to deform by the protective casing, thereby avoiding a circumstance in which the deformation of the lens makes the mobile terminal unable to accurately recognize an obstacle.

Abstract: A barcode image recognition method includes the following steps: capturing at least one barcode to generate a preview image, the preview image having at least one barcode image of the at least one barcode; decoding the barcode image to obtain barcode information and a plurality of vertex coordinates of the barcode image; caching the barcode information of the barcode image; forming a plurality of image boundaries of the barcode image with the plurality of vertex coordinates of the barcode image; generating a detection beeline from a specified point to a side edge of the preview image; determining the number of intersections of the plurality of image boundaries of the barcode image and the detection beeline; identifying the barcode image with odd number of intersections from the at least one barcode image as a target image; and outputting the barcode information of the target image.

Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure located on the substrate, a second type semiconductor structure located on the first type semiconductor structure, an active structure located between the first type semiconductor structure and the second type semiconductor structure, a plurality of contact portions disposed between the first type semiconductor structure and the substrate, and a first conductive oxide layer, a second conductive oxide layer, a first insulating layer and a second insulating layer. The plurality of contact portions is separated from each other, and one of them includes a semiconductor and has a side wall. The first conductive oxide layer contacts the contact portion, and the second conductive oxide layer contacts the first conductive oxide layer. The first insulating layer contacts the side wall. The second insulating layer is disposed between the first insulating layer and the second conductive oxide layer.

Abstract: A semiconductor structure according to the present disclosure includes a circuit region disposed over a substrate and a seal ring region disposed over the substrate and completely surrounding the circuit region. The circuit region includes first fins, second fins, n-type epitaxial structures over the first fins, and p-type epitaxial structures over the second fins. The seal ring region includes fin rings extending completely around the circuit region, epitaxial rings disposed over and extending parallel to the fin rings. All of the epitaxial rings over all of the fin rings in the seal ring region are p-type epitaxial rings.

Abstract: A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.

Abstract: A transparent antenna includes a substrate, an antenna grid layer, and a ground grid layer. The substrate has an electrically conductive hole extending from two opposite surfaced of the substrate. The antenna grid layer is formed on a surface of the substrate. The antenna grid layer includes a feeding portion and a transmission portion. The ground grid layer is formed on another surface of the substrate. The ground grid layer is coupled to the feeding portion of the antenna grid layer via the electrically conductive hole. An offset distance between a projection of a gridline of the antenna grid layer on the first surface and a projection of a gridline of the ground grid layer on the first surface is smaller than or equal to half of a difference between a line width of the antenna grid layer and a line width of the ground grid layer.

Abstract: An electronic device configured with a microphone, a voice interaction wake-up method executed by an electronic device equipped with a microphone, and a computer-readable medium, the electronic device comprising a memory and a central processing unit, wherein the memory stores computer-executable instructions, and when executed by the central processing unit, the computer-executable instructions perform the following operations: analyzing a sound signal collected by a microphone, identifying whether the sound signal contains speech spoken by a person and whether it contains wind noise sounds generated by airflows hitting the microphone as a result of the speech spoken by the person, and in response to determining that the sound signal contains sound spoken by the person and contains wind noise sounds generated by airflows hitting the microphone as a result of the speech spoken by the user, processing the sound signal as speech input by the user.

Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.

Abstract: The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.

Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes an interconnect structure that includes a first metal line, a second metal line, a third metal line, a fourth metal line, and a fifth meal line extending along a first direction, a first group of lateral connectors disposed between the second metal line and the third metal line or between the fourth metal line and the fifth metal line, and a second group of lateral connectors disposed between the first metal line and the second metal line or between the third metal line and the fourth metal line.

Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.

Abstract: An audio parameter optimizing method and a computing apparatus related to audio parameters. In the method, sound features of multiple sound signals are obtained. A wide dynamic range compression (WDRC) parameter corresponding to each of the sound signals is determined. Multiple data sets including the sound features and the corresponding WDRC parameters of the sound signals are created. The data sets are used to train a neural network, so as to generate a parameter inference model. The parameter inference model is configured to determine the WDRC parameter of a to-be-evaluated signal. Accordingly, a proper parameter could be provided.

Abstract: The present disclosure describes novel compounds, or their pharmaceutically acceptable salts, pharmaceutical compositions containing them, and their medical uses. Compounds of the disclosure have activity as dual modulators of Janus kinase (JAK), alone, or in combination with one or more of an additional mechanism, including a tyrosine kinase, such as TrkA or Syk, and PDE4, and are useful in the in the treatment or control of inflammation, auto-immune diseases, cancer, and other disorders and indications where modulation of JAK would be desirable. Also described herein are methods of treating inflammation, auto-immune diseases, cancer, and other conditions susceptible to inhibition of JAK and PDE4 by administering a compound herein described.

Abstract: A display panel includes a plurality of driving electrode regions and a plurality of wiring regions connected between the driving electrode regions. A (2n?1)th wiring region extended from a (2n?1)th driving electrode region toward a (2n)th driving electrode region has a wiring extending direction forming a first included angle with an arrangement direction, and a (2n)th wiring region extended from the (2n)th driving electrode region toward a (2n+1)th driving electrode region has a wiring extending direction forming a second included angle with the arrangement direction, and a (2n+1)th wiring region extended from the (2n+1)th driving electrode region toward a (2n+2)th driving electrode region has a wiring extending direction forming a third included angle with the arrangement direction, wherein n is a positive integer. At least one of the first included angle, the second included angle and the third included angle is positive and at least one of them is negative.

Abstract: A composition, composite material, and copper clad laminate are provided. The composition includes 100 parts by weight of a compound having two epoxy groups, 20-80 parts by weight of a compound having at least two phenolic hydroxy groups, and 0.01-1.5 parts by weight of an ionic liquid. The ionic liquid is not imidazolium ionic liquid.

Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a circuit region and a seal ring region around the circuit region, first active regions of a first width disposed in the circuit region, second active regions of a second width disposed in the seal ring region, first gate structures disposed on the first active regions, and second gate structures disposed on longitudinal edges of the second active regions. The first gate structures are longitudinally oriented to be orthogonal with the first active regions. The second gate structures are longitudinally oriented to be in parallel with the second active regions. The second width is greater than the first width.

Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

Abstract: A touch control circuit for use in a display device includes: a plurality of analog-to-digital converters and a controller. Each of the analog-to-digital converters is coupled to at least one of a plurality of touch sensing electrodes and at least one of a plurality of source drivers of the display device. At least one of the analog-to-digital converters is configured to generate a first measured digital code according to an output voltage outputted by at the least one of the source drivers. The controller is coupled to the analog-to-digital converters, and configured to compare the first measured digital code with an input digital code that the output voltage of the at the least one of the source drivers corresponds to, thereby to generate a first safety detection result regarding the at least one of the source drivers.

Abstract: A system includes a storage tank, a first gas injection unit, a second gas injection unit, a concentration sensor, a dynamic control unit, and a data processing and analysis module. The storage tank is configured to hold a chemical liquid used in etching processes. The first gas injection unit includes a first gas pipe configured to inject a first gas into the storage tank, and a first adjustable valve mounted on the first gas pipe. The second gas injection unit includes a second gas pipe configured to inject a second gas into the storage tank, and a second adjustable valve mounted on the second gas pipe. The concentration sensor is connected to the storage tank. The dynamic control unit electrically connected to the first and second adjustable valves and the concentration sensor. The data processing and analysis module integrated with the dynamic control unit.