Abstract: A test method for performing a factory test on an automotive IC includes: performing a logic test on the automotive IC by sending one or more logic test input signals to the automotive IC to generate one or more logic test output signals; while the automotive IC is generating the one or more logic test output signals, utilizing a safety detection circuit within the automotive IC to determine whether at least one analog voltage of an analog circuit block of the automotive IC falls within a predetermined range to generate an analog test result; and determining whether the automotive IC passes the factory test according to at least the logic test output signals and the analog test result.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element and a heat dissipation structure covering the electronic element are disposed on a carrier structure, and the electronic element is covered with a cladding layer. The heat dissipation structure has convex portions facing the carrier structure, so that the bonding area between the heat dissipation structure and the cladding layer is increased via the convex portions, thereby preventing the problem of peeling from occurring to the heat dissipation structure.

Abstract: A semiconductor structure includes a circuit region and a seal ring region. The seal ring region includes a stack of first and second semiconductor layers alternately stacked. The stack forms a continuous ring surrounding the circuit region. A gate structure is disposed on a top surface of the stack. A contour of a top surface of the gate structure is fully within a contour of the top surface of the stack in a top view of the semiconductor structure.

Abstract: The present disclosure provides a semiconductor structure that includes dielectric layers disposed over a semiconductor substrate; and a seal ring structure formed in the dielectric layers and distributed in multiple metal layers. The seal ring structure further includes first metal lines of a metal layer disposed in a first area and longitudinally oriented along a first direction; second metal lines of the metal layer disposed in a second area and longitudinally oriented along the first direction; and metal bars of the metal layer disposed in the first area and longitudinally oriented along a second direction, the metal bars connecting the first metal lines.

Abstract: Semiconductor structures and method of forming the same are provided. A method according to the present disclosure includes providing an intermediate structure that includes an opening, conformally depositing a metal liner over the opening, depositing a dummy fill material over the metal liner, recessing the dummy fill material such that a portion of the metal liner is exposed, removing the exposed portion of the metal liner, removing the recessed dummy fill material, and after the removing of the recessed dummy fill material, depositing a metal fill layer over the opening.

Abstract: Provided herein are compounds comprising modified oligonucleotides targeted to microRNAs, wherein the modified oligonucleotides are designed to avoid off-target effects.

Abstract: Disclosed are a heat-electricity discrete power module with two-way heat-dissipation ceramic substrates and a manufacturing method of the same, including: two double-sided metal-clad ceramic substrates, a power transistor die, and an insulation sealant; each double-sided metal-clad ceramic substrate including a ceramic insulation layer, a three-dimensional conductive layer formed on the first ceramic insulation layer and facing the opposite three-dimensional conductive layer to constitute an electrical circuit, and a thermally-conductive metallic layer opposite and insulated from the three-dimensional conductive layer, respectively; electrodes of each power transistor die are electrically conductively connected to the three-dimensional conductive layer, and their upper and lower surfaces are thermally conductively connected to respective three-dimensional conductive layers; circuit components are additionally mounted on the three-dimensional conductive layers; at least one conductive post is formed between th

Abstract: A method includes forming a first de-bond structure over a first substrate, where forming the first de-bond structure includes depositing a first de-bond layer over the first substrate, depositing a first silicon layer over the first de-bond layer, depositing a second de-bond layer over the first silicon layer, and depositing a second silicon layer over the second de-bond layer, epitaxially growing a first multi-layer stack over the first de-bond structure, bonding the first multi-layer stack to a second multi-layer stack, and performing a first laser annealing process to ablate the first silicon layer and portions of the first de-bond layer and the second de-bond layer in order to de-bond the first substrate from the first multi-layer stack.

Abstract: A modular heat exchanger includes: two finned heat sinks, each finned heat sink has multiple guiding plates and a mounting recess; a securing assembly for securing the two finned heat sinks; a heat conduction pipe mounted in the mounting recesses; multiple modular blocks linearly arranged, and each modular block has multiple inlet through holes and multiple outlet through holes; multiple water pipes, each water pipe has two ends mounted through the inlet through holes and the outlet through holes respectively; and multiple coolers mounted to an outer sidewall defined on at least one of the modular blocks. It is convenient to assemble, disassemble or expand the modular heat exchanger, so as to improve performance of the modular heat exchanger. When one of the coolers fails, it is able to reach and detach said failed cooler by disassembling some parts of the modular heat exchanger, which is convenient.

Abstract: A method includes forming a bonding structure that contains thermal conductive vias (also termed as thermal vias, thermal conductive pillars, or thermal pillars) on a semiconductor structure. The thermal vias, with material thermal conductivity greater than about 10 W/m·K, are embedded in the bonding structure that provides a quick dissipation path of heat from thermal hotspot regions into a substrate.

Abstract: A semiconductor structure according to the present disclosure includes a circuit region disposed over a substrate and a seal ring region disposed over the substrate and completely surrounding the circuit region. The circuit region includes first fins, second fins, n-type epitaxial structures over the first fins, and p-type epitaxial structures over the second fins. The seal ring region includes fin rings extending completely around the circuit region, epitaxial rings disposed over and extending parallel to the fin rings. All of the epitaxial rings over all of the fin rings in the seal ring region are p-type epitaxial rings.

Abstract: A power connection assembly includes a housing, a plug, and a first and a second conductive member. The housing has a first opening. The plug is disposed in the housing, and includes a first rotating base, and a first and a second electrode terminal. The first rotating base is movably fitted into the first opening. The first and the second electrode terminal penetrate through the first rotating base to form a first and a second contact portion. The first conductive member includes a first clamping portion that includes two second elastic sheets. Each second elastic sheet has a first and a second elastic segment. The first elastic segment is L-shaped, and the second elastic segment is cylindrical. The second elastic segments of the two second elastic sheets are configured to clamp the first electrode terminal, so that the first electrode terminal electrically contacts the first conductive member.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.

Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a device region, an inner ring surrounding the device region, an outer ring surrounding the inner ring, a first corner area between an outer corner of the inner ring and an inner corner of the outer ring, and a second corner area disposed at an outer corner of the outer ring. The first corner area includes a first active region including a channel region and a source/drain region, a first gate structure over the channel region of the first active region, and a first source/drain contact over the source/drain region of the first active region. The first source/drain contact continuously extends from a first edge of the first corner area to a second edge of the first corner area.

Abstract: A calibration method for machine tools comprises: providing a workpiece on a machine tool; rotating the workpiece around a first rotation axis parallel to a main shaft of the machine tool and processing the workpiece by a first machining mode; measuring a first dimensional error of a shape of the workpiece along directions of first and second linear axes perpendicular to the first rotation axis; calculating a positional error of the first rotation axis according to the first dimensional error; rotating the workpiece around a second rotation axis perpendicular to the main shaft and processing the workpiece by a different second machining mode; measuring a second dimensional error of the shape of the workpiece along a direction of a third linear axis perpendicular to the second rotation axis; calculating a positional error of the second rotation axis according to the second dimensional error.

Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.

Abstract: A method for scanning multiple barcodes is provided. A tag template, recording a predetermined number of barcode forms and relative configuration orientations of the predetermined number of barcode forms, is read. The tag is photographed to obtain a tag image of the tag, wherein a surface of the tag includes a plurality of barcodes. The tag image is analyzed to obtain barcode patterns of the barcodes in the tag image, and barcode types and relative coordinates of the barcode patterns. The barcode types of the barcode patterns and the relative coordinates of the barcode patterns are detected according to the tag template to identify from the barcode patterns a predetermined number of barcode patterns to be outputted matching the tag template. The barcode patterns to be outputted are decoded to obtain information respectively represented by the barcode patterns to be outputted, and the information obtained is outputted.