Patents by Inventor Chun-Yu Chen

Chun-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240207823
    Abstract: The present invention relates to a layered catalytic article, particularly useful for three-way conversion, which comprises a) atop layer comprising a palladium (Pd) component, a platinum (Pt) component and a rhodium (Rh) component, wherein the palladium component, the platinum component and the rhodium component are present in supported forms, and wherein at least part of the platinum component and at least part of the rhodium component are supported together on one or more supports; b) a bottom layer comprising a palladium component in a supported form as the only platinum group metal component; and c) a substrate, on which the top layer and bottom layer are carried, wherein the palladium components are loaded in the top layer and in the bottom layer at a ratio of higher than 1:1, calculated as palladium element, and also to an exhaust treatment system comprising the same.
    Type: Application
    Filed: April 20, 2022
    Publication date: June 27, 2024
    Applicant: BASF Corporation
    Inventors: Wei Liang Wang, Xiaolai Zheng, Chun Yu chen, Attilio Siani, Pascaline Tran
  • Publication number: 20240176734
    Abstract: The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.
    Type: Application
    Filed: September 15, 2023
    Publication date: May 30, 2024
    Applicant: Silicon Motion, Inc.
    Inventor: Chun-Yu CHEN
  • Patent number: 11990547
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: May 21, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yu Chen, Bo-Lin Huang, Jhong-Yi Huang, Keng-Jen Lin, Yu-Shu Lin
  • Publication number: 20240163072
    Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.
    Type: Application
    Filed: February 2, 2023
    Publication date: May 16, 2024
    Inventors: YU-CHIEH HSU, LING-WEI KE, CHUN-YU CHEN, HONG-YUN WEI
  • Publication number: 20240154703
    Abstract: A signal processing system includes a first transceiver unit, a second transceiver unit, a protocol analysis circuit, a system chip, and a network unit. The first transceiver unit can transceive a first optical signal and a first electrical signal. The second transceiver unit can transceive a second optical signal and a second electrical signal. The protocol analysis circuit can process the first electrical signal and an analysis signal related to the first optical signal. The system chip can process the analysis signal, the second electrical signal, a first operation signal and a second operation signal. The network unit can transceive the first operation signal and the second operation signal, and transceive a first network signal and a second network signal between the network unit and a user device. The system chip and the network unit can process signals related to the first optical signal and the second optical signal.
    Type: Application
    Filed: September 18, 2023
    Publication date: May 9, 2024
    Applicant: Gemtek Technology Co., Ltd.
    Inventors: Hung-Wen Chen, Chih-Sien Yao, Chun-Yu Chen
  • Publication number: 20240139938
    Abstract: A control method of a robotic arm is provided. The control method includes: setting a detection circuit, a comparing circuit and a switching circuit. The detection circuit detects the motion of the robotic arm to generate a detection signal. The comparing circuit compares the detection signal with a low threshold region and compares the detection signal with a high threshold region to generate a comparison signal. The switching circuit switches the robotic arm to a first motion mode or a second motion mode according to the comparison signal.
    Type: Application
    Filed: April 19, 2023
    Publication date: May 2, 2024
    Inventors: Chun-Yu CHEN, Shih-Wei WANG
  • Patent number: 11846729
    Abstract: A virtual reality positioning device including a casing, a plurality of lenses, and a plurality of optical positioning components is provided. The casing has a plurality of holes. The lenses are installed in the holes, respectively, where a field angle of each of the lenses is greater than or equal to 120 degrees and less than or equal to 160 degrees, and the lenses include convex lenses or Fresnel lenses. The optical positioning components are installed in the casing and aligned to the lenses, respectively. In addition, a virtual reality positioning system and manufacturing method of a virtual reality positioning device are provided.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: December 19, 2023
    Assignee: Acer Incorporated
    Inventors: Li Lin, Ker-Wei Lin, Chun-Ta Chen, Chun-Yu Chen, Hao-Ming Chang, Chun-Hsien Chen, Shih-Ting Huang, Hui-Yen Wang
  • Publication number: 20230399420
    Abstract: Disclosed are support-activators and catalyst compositions comprising the support-activators for polymerizing olefins in which the support-activator includes a clay heteroadduct, also termed a composite, prepared from a colloidal phyllosilicate such as a colloidal smectite clay, which is chemically-modified with a surfactant. In an aspect, the clay composite can comprise the contact product of a colloidal smectite clay and a surfactant in a liquid carrier, but in the absence of any other reactant such as a cationic polymetallate, and their use as support-activators for metallocene precatalysts is also described. The use of surfactants with cationic polymetallates in forming clay-composites is also described.
    Type: Application
    Filed: May 24, 2023
    Publication date: December 14, 2023
    Applicant: Formosa Plastics Corporation, U.S.A.
    Inventors: Kevin Chung, Michael D. Jensen, Yiqun Fang, Casey Zamzow, Charles R. Johnson, II, Mary Lou Cowen, Jenny Chun-Yu Chen
  • Publication number: 20230395680
    Abstract: A method includes providing a structure having a substrate and first and second semiconductor layers alternately stacked one over another above the substrate, etching the first and the second semiconductor layers to form a first continuous ring in a seal ring region of the structure, and forming an isolation structure adjacent the first continuous ring in the seal ring region. The method further includes forming a dummy gate structure that is disposed directly above the first continuous ring and completely within a boundary of the first continuous ring from a top view, growing first and second epitaxial features sandwiching the dummy gate structure, removing the dummy gate structure, resulting in a gate trench that exposes a topmost layer of the first semiconductor layers and does not expose side surfaces of the first and second semiconductor layers, and depositing a gate structure in the gate trench.
    Type: Application
    Filed: June 5, 2022
    Publication date: December 7, 2023
    Inventors: Chun Yu Chen, Yen Lian Lai
  • Publication number: 20230397502
    Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a device region, an inner ring surrounding the device region, an outer ring surrounding the inner ring, a first corner area between an outer corner of the inner ring and an inner corner of the outer ring, and a second corner area disposed at an outer corner of the outer ring. The first corner area includes a first active region including a channel region and a source/drain region, a first gate structure over the channel region of the first active region, and a first source/drain contact over the source/drain region of the first active region. The first source/drain contact continuously extends from a first edge of the first corner area to a second edge of the first corner area.
    Type: Application
    Filed: July 20, 2023
    Publication date: December 7, 2023
    Inventors: Chun Yu Chen, Yen Lian Lai
  • Publication number: 20230395533
    Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a circuit region and a seal ring region around the circuit region; first active regions of a first width W1 formed in the circuit region; second active regions of a second width W2 formed in the seal ring region; first gate stacks disposed on the first active regions in the circuit region and extending to isolation features; and second gate stacks disposed on the second active regions in the seal ring region and completely landing on the second active regions. The second width is greater than the first width, and each of the second active regions is a continuous ring shape to enclose the circuit region.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Chun Yu CHEN, Yen Lian LAI
  • Patent number: 11802773
    Abstract: A method for navigating and route planning based on a HD map and with reference to other electronic devices moving along a similar route includes setting a start location and an end location; planning at least one navigation route based on the start location and the end location; acquiring locations of own electronic device and of co-travelling external electronic devices based on the HD map; acquiring speeds of the external electronic devices and selecting those moving at low speed; identifying moving directions of the slow-speed target electronic devices; and re-planning and resetting the at least one navigation route when the moving directions of the target electronic devices intersected with a direction of the lane. An electronic device and a server applying the method are also disclosed.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: October 31, 2023
    Assignee: Mobile Drive Netherlands B.V.
    Inventors: Hsien-Chi Tsai, Chun-Yu Chen
  • Publication number: 20230330638
    Abstract: Described herein is a layered catalytic article which includes a) a top layer including a front zone and a rear zone, where the front zone includes a palladium component and a rhodium component, supported individually or together on a support, and the rear zone includes a platinum component, a rhodium component and optionally a palladium component, supported individually or together on a support; b) a bottom layer including a platinum component and a palladium component supported individually or together on a support; and c) a substrate. Also described herein are an exhaust treatment system including the layered catalytic article and a method of using the layered catalytic article for abatement of hydrocarbons, carbon monoxide and nitrogen oxides in an exhaust stream.
    Type: Application
    Filed: September 9, 2021
    Publication date: October 19, 2023
    Inventors: Chun Yu CHEN, Xiaolai ZHENG, Wei Liang WANG, Attilio SIANI, Pascaline TRAN
  • Patent number: 11728338
    Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a device region, an inner ring surrounding the device region, an outer ring surrounding the inner ring, a first corner area between an outer corner of the inner ring and an inner corner of the outer ring, and a second corner area disposed at an outer corner of the outer ring. The first corner area includes a first active region including a channel region and a source/drain region, a first gate structure over the channel region of the first active region, and a first source/drain contact over the source/drain region of the first active region. The first source/drain contact continuously extends from a first edge of the first corner area to a second edge of the first corner area.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Yu Chen, Yen Lian Lai
  • Publication number: 20230232079
    Abstract: An optical device includes a light guide unit, an optical path conversion unit and an optical transceiver unit. The light guiding unit is connected to the optical fiber and is suitable for transmitting optical signals. The optical path conversion unit is connected to the light guide unit, and is suitable for receiving optical signals and changing the optical path of the optical signals. It is used in the optical transceiver unit for the configuration of two receiving parts and two transmitting parts, which can support the same optical path at the same time with use of two sets of communication protocol systems and the cable TV protocol system.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 20, 2023
    Inventors: Chin-Tsung WU, Kuei Hsiang CHENG, Chun Yu CHEN
  • Patent number: 11694544
    Abstract: A traffic safety control method is provided. The method includes determining whether there is an intersection in front of a vehicle. When there is the intersection in front of the vehicle, a driving direction of the vehicle at the intersection is predicted according to a plurality of lane positions of the vehicle that are continuously obtained. A message is transmitted once the predicted driving direction is determined to be conflicting with a traffic rule of the intersection.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: July 4, 2023
    Assignee: Mobile Drive Netherlands B.V.
    Inventors: Hsien-Chi Tsai, Chun-Yu Chen
  • Publication number: 20230194880
    Abstract: A pair of augmented reality glasses including a projection device and a waveguide is provided. The projection device is configured to provide a collimated beam. The waveguide has a plurality of free form surfaces. Distances between each free form surface and the projection device are different from each other. The collimated beam progresses to and reflects off these free form surfaces in sequence, and then enters eyes of the user.
    Type: Application
    Filed: April 1, 2022
    Publication date: June 22, 2023
    Applicant: Acer Incorporated
    Inventors: Tsung-Wei Tu, Yi-Jung Chiu, Shih-Ting Huang, Yen-Hsien Li, Chun-Yu Chen
  • Publication number: 20230175782
    Abstract: A modular heat exchanger includes: two finned heat sinks, each finned heat sink has multiple guiding plates and a mounting recess; a securing assembly for securing the two finned heat sinks; a heat conduction pipe mounted in the mounting recesses; multiple modular blocks linearly arranged, and each modular block has multiple inlet through holes and multiple outlet through holes; multiple water pipes, each water pipe has two ends mounted through the inlet through holes and the outlet through holes respectively; and multiple coolers mounted to an outer sidewall defined on at least one of the modular blocks. It is convenient to assemble, disassemble or expand the modular heat exchanger, so as to improve performance of the modular heat exchanger. When one of the coolers fails, it is able to reach and detach said failed cooler by disassembling some parts of the modular heat exchanger, which is convenient.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 8, 2023
    Inventors: Tsung-Ming CHEN, Chun-Yu CHEN
  • Patent number: D1009865
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: January 2, 2024
    Assignee: Acer Incorporated
    Inventors: Chun-Yu Chen, Ker-Wei Lin, Chun-Ta Chen
  • Patent number: D1023935
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Ya-Hao Chan, Yi-Heng Lee, Ming-Cheng Wu, Chun-Yu Chen