Abstract: A semiconductor structure with dual side seal rings is provided. A semiconductor structure according to the present disclosure include a substrate including a device region and a ring region surrounding the device region, a frontside interconnect structure disposed over the substrate and including a frontside interconnect region and a frontside seal ring region, and a backside interconnect structure disposed below the substrate and including a backside interconnect region and a backside seal ring region. The frontside interconnect region is disposed over the device region and the backside interconnect region is disposed below the device region. The frontside seal ring region is disposed over the ring region and the backside seal ring region is disposed below the ring region.

Abstract: A power connection assembly includes a housing, a plug, and a first and a second conductive member. The housing has a first opening. The plug is disposed in the housing, and includes a first rotating base, and a first and a second electrode terminal. The first rotating base is movably fitted into the first opening. The first and the second electrode terminal penetrate through the first rotating base to form a first and a second contact portion. The first conductive member includes a first clamping portion that includes two second elastic sheets. Each second elastic sheet has a first and a second elastic segment. The first elastic segment is L-shaped, and the second elastic segment is cylindrical. The second elastic segments of the two second elastic sheets are configured to clamp the first electrode terminal, so that the first electrode terminal electrically contacts the first conductive member.

Abstract: A method of processing a semiconductor wafer is provided. The method includes installing upper lid. The installation of the upper lid includes placing an inlet manifold on a water box; inserting a jig into a lower gas channel in the water box and inserting into an upper gas channel in the inlet manifold; fastening the water box to the inlet manifold; and removing the jig after the water box engaging with the inlet manifold. The method also includes connecting a shower head on a lower side of the water box; and connecting the upper lid to a housing. The method further includes placing a semiconductor wafer into the housing. In addition, the method includes supplying a process gas over the semiconductor wafer through the upper gas channel, the lower gas channel and the shower head.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; and a seal ring region enclosing a circuit region disposed over the substrate. The seal ring region further includes a fin ring protruding from the substrate having a first width; an isolation ring disposed over the substrate and adjacent to the fin ring; a gate ring disposed over the fin ring having a second width, wherein the second width is less than the first width; an epitaxial ring disposed between the fin ring and the isolation ring; and a contact ring lands on the epitaxial ring and the isolation ring. Each of the fin ring, the isolation ring, the epitaxial ring, and the contact ring extends parallel to each other and fully surrounds the circuit region to form a closed loop.

Abstract: Integrated circuit (IC) chips are provided. An IC chip according to the present corner area between an outer corner of the device region and an inner corner of the ring region. The ring region includes a first active region extending along a first direction, a first source/drain contact disposed partially over the first active region and extending along the first direction, and first gate structures disposed completely over the first active region and each extending lengthwise along the first direction. The corner area includes a second active region extending along a second direction that forms an acute angle with the first direction, a second source/drain contact disposed partially over the second active region and extending along the second direction, and second gate structures disposed over the second active region and each extending along the first direction.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes an interconnect structure that includes a first metal line, a second metal line, a third metal line, a fourth metal line, and a fifth meal line extending along a first direction, a first group of lateral connectors disposed between the second metal line and the third metal line or between the fourth metal line and the fifth metal line, and a second group of lateral connectors disposed between the first metal line and the second metal line or between the third metal line and the fourth metal line.

Abstract: A semiconductor structure includes a device region and a seal structure surrounding the device region. The seal structure includes an outer ring surrounding the device region and a buffer region disposed between the outer ring and the device region. The buffer region includes a first portion having a number of first gate structures extending lengthwise along a first direction and a second portion having a number of second gate structures extending lengthwise along the first direction. The second portion of the buffer region is disposed between the first portion of the buffer region and the outer ring. Along a second direction that is substantially perpendicular to the first direction, a width of each of the first gate structures is greater than a width of each of the second gate structures.

Abstract: A semiconductor structure includes a substrate; a seal ring region around a circuit region over the substrate, wherein the seal ring region includes a sealing region and a transition region, and wherein the transition region is disposed between the sealing region and the circuit region; and a stack of metal layers disposed over the circuit region, the transition region and the sealing region. A metal layer of the stack of metal layers includes metal seal rings disposed in the sealing region including a first section along a first direction and a second section along a second direction, wherein the second direction is substantially perpendicular to the first direction; and metal transition lines disposed in the transition region along the first section and the second section, wherein the metal transition lines are oriented lengthwise along the first direction.

Abstract: The present disclosure provides a semiconductor structure that includes dielectric layers disposed over a semiconductor substrate; and a seal ring structure formed in the dielectric layers and distributed in multiple metal layers. The seal ring structure further includes first metal lines of a metal layer disposed in a first area and longitudinally oriented along a first direction; second metal lines of the metal layer disposed in a second area and longitudinally oriented along the first direction; and metal bars of the metal layer disposed in the first area and longitudinally oriented along a second direction, the metal bars connecting the first metal lines.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a substrate and a first interconnect layer over the substrate. The first interconnect layer includes a first device region and a first ring region surrounding the first device region. The first ring region includes a first wall fully surrounding the first device region and a second wall fully surrounding the first device region and the first wall. The first wall is spaced apart from the second wall by a first intermetal dielectric layer and at least one first dummy metal line along an edge of the first device region. The first wall is spaced apart from the second wall only by the first intermetal dielectric layer around a corner of the first device region.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a substrate that has a device region and a ring region surrounding the device region, an interconnect structure disposed on the substrate, a first passivation layer disposed over the interconnect structure, a first contact via ring embedded in the first passivation layer, a first contact pad ring disposed on the first contact via ring and the first passivation layer, a second passivation layer disposed over the first contact pad ring, and a polymer layer disposed on a portion of the second passivation layer. The first contact via ring and the first contact pad ring completely surround the device region.

Abstract: A semiconductor structure according to the present disclosure includes a circuit region disposed over a substrate and a seal ring region disposed over the substrate and completely surrounding the circuit region. The circuit region includes first fins, second fins, n-type epitaxial structures over the first fins, and p-type epitaxial structures over the second fins. The seal ring region includes fin rings extending completely around the circuit region, epitaxial rings disposed over and extending parallel to the fin rings. All of the epitaxial rings over all of the fin rings in the seal ring region are p-type epitaxial rings.

Abstract: A method for providing driving assistance based on a HD map includes acquiring information such as position of a vehicle and timing, and acquiring a speed of the vehicle based on the manner of driving, and acquiring distance an intersection in front of the vehicle and information from a HD map such as traffic light intersection ahead. Deciding such as whether the vehicle can pass through the intersection based on the speed of the vehicle, intersection distance, and the traffic light information and prompting and/or controlling the vehicle if it is determined that passage through is not possible. A vehicle-mounted apparatus applying the method is also disclosed.

Abstract: A semiconductor structure includes a substrate, a circuit region, and a seal ring surrounding the circuit region. The circuit region includes two first source/drains, first semiconductor layers connecting the two first source/drains, and a first gate disposed between the two first source/drains and wrapping around each of the first semiconductor layers. The seal ring includes two epitaxially grown semiconductor structures, second semiconductor layers, third semiconductor layers, and a second gate. The second and the third semiconductor layers are alternately stacked one over another to form a stack of layers. A topmost layer of the stack is one of the third semiconductor layers. The second gate is disposed between the two epitaxially grown semiconductor structures and above the topmost layer of the stack. The first and the third semiconductor layers include a first semiconductor material. The second semiconductor layers include a second semiconductor material different from the first semiconductor material.

Abstract: Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a device region, an inner ring surrounding the device region, an outer ring surrounding the inner ring, a first corner area between an outer corner of the inner ring and an inner corner of the outer ring, and a second corner area disposed at an outer corner of the outer ring. The first corner area includes a first active region including a channel region and a source/drain region, a first gate structure over the channel region of the first active region, and a first source/drain contact over the source/drain region of the first active region. The first source/drain contact continuously extends from a first edge of the first corner area to a second edge of the first corner area.

Abstract: A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

Abstract: A traffic safety control method is provided. The method includes obtaining first related information of a road when a vehicle is traveling on a road. Second related information is detected using a detecting device of the vehicle when the first related information indicates that there is the intersection in front of the vehicle on the road. The vehicle is controlled according to the first related information and the second related information.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.

Abstract: Recombinant polynucleotides and vectors containing an engineered (artificial) exon-intron-exon gene structure in a transgene are provided, which undergoes splicing when it is expressed in a target cell.

Abstract: The present invention discloses an optical path length adjusting device, having a body, an optical path moving shaft, and an optical path adjusting screw, an auxiliary rod, and a connecting plate. By adjusting the optical path moving shaft, the optical path adjusting rod, and the auxiliary rod, and the connecting plate, the optical path can be adjusted after the light injected from the optical fiber into the optical path adjusting device. The present invention further comprises at least a bearing to stably drive a single direction of movement. The optical path length adjusting device will not cause angular deviation in the process of adjusting the optical path.