Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.

Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

Abstract: Methods for isolating two adjacent transistors are disclosed. A substrate has a first semiconducting fin on a first region and a second semiconducting fin on a second region, and the first semiconducting fin and the second semiconducting fin contact each other at a jog region. A dummy gate within or adjacent the jog region is removed to expose a portion of the first semiconducting fin and form an isolation volume. Etching is performed to remove the exposed portion of the first semiconducting fin and create a trench in the substrate. The trench and the isolation volume are filled with at least one dielectric material to form an electrically isolating structure between the first region and the second region. Additional dummy gates in each region can be removed and replaced with an electrically conductive material to form two adjacent transistors electrically isolated from each other.

Abstract: Methods for revitalizing components of a plasma processing apparatus that includes a sensor for detecting a thickness or roughness of a peeling weakness layer on a protective surface coating of a plasma processing tool and/or for detecting airborne contaminants generated by such peeling weakness layer. The method includes detecting detrimental amounts of peeling weakness layer buildup or airborne concentration of atoms or molecules from the peeling weakness layer, and initiating a revitalization process that bead beats the peeling weakness layer to remove it from the component while maintaining the integrity of the protective surface coating.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: A solar cell module includes a first substrate, a second substrate, at least one cell unit, a first packaging film, a second packaging film, a first protective layer, a second protective layer, and a plurality of support members. The first substrate and the second substrate are disposed opposite to each other. The cell unit is disposed between the first substrate and the second substrate. The first packaging film is disposed between the cell unit and the first substrate. The second packaging film is disposed between the cell unit and the second substrate. The first protective layer is disposed between the cell unit and the first packaging film. The second protective layer is disposed between the cell unit and the second packaging film. The support members are respectively disposed between the first packaging film and the second packaging film and surround at least two opposite sides of the cell unit.

Abstract: A continuous metal on diffusion edge (CMODE) may be used to form a CMODE structure in a semiconductor device after a replacement gate process that is performed to replace the polysilicon dummy gate structures of the semiconductor device with metal gate structures. The CMODE process described herein includes removing a portion of a metal gate structure (as opposed to removing a portion of a polysilicon dummy gate structure) to enable formation of the CMODE structure in a recess left behind by removal of the portion of the metal gate structure.

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

Abstract: A method includes: positioning a wafer on an electrostatic chuck of a physical vapor deposition apparatus, the wafer including an opening exposing a conductive feature; setting a temperature of the wafer to a room temperature; forming a tungsten thin film in the opening by the physical vapor deposition apparatus, the tungsten thin film including a bottom portion that is on an upper surface of the conductive feature exposed by the opening, a top portion that is on an upper surface of a dielectric layer through which the opening extends and a sidewall portion that is on a sidewall of the dielectric layer exposed by the opening; removing the top portion and the sidewall portion of the tungsten thin film from over the opening; and forming a tungsten plug in the opening on the bottom portion by selectively depositing tungsten by a chemical vapor deposition operation.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.

Abstract: A content channel generation device comprises a resource unit assignment circuit, for assigning scheduled station(s) as node(s) of a full binary tree according to a search algorithm; a node computing circuit, for determining first node connection information of the full binary tree, and to determine second node connection information of a smallest full binary tree according to a smallest binary tree algorithm and the first node connection information; a load balance circuit, for determining user field numbers corresponding to content channels according to a load balance function and the second node connection information; a user field generation circuit, for generating a traversal result of the smallest full binary tree according to a traversal algorithm and the second node connection information, and for generating user fields corresponding to the content channels according to the traversal result, to generate the content channels.

Abstract: A calibration method for machine tools comprises: providing a workpiece on a machine tool; rotating the workpiece around a first rotation axis parallel to a main shaft of the machine tool and processing the workpiece by a first machining mode; measuring a first dimensional error of a shape of the workpiece along directions of first and second linear axes perpendicular to the first rotation axis; calculating a positional error of the first rotation axis according to the first dimensional error; rotating the workpiece around a second rotation axis perpendicular to the main shaft and processing the workpiece by a different second machining mode; measuring a second dimensional error of the shape of the workpiece along a direction of a third linear axis perpendicular to the second rotation axis; calculating a positional error of the second rotation axis according to the second dimensional error.

Abstract: An optical biometer includes a light-source module, a light-splitting module, a reference-arm, a sensing-arm and a sensing module. The light-source module emits incident-light. The light-splitting module, disposed corresponding to light-source module, divides the incident-light into reference light and sensing light. The reference-arm, disposed corresponding to light-splitting module, generates a first reflected-light according to the reference light. The sensing-arm, disposed corresponding to the light-splitting module, emits the sensing light to the eye and receives a second reflected-light from the eye. The sensing module generates a sensing result according to the first reflected-light and second reflected-light. In a first mode, the sensing light is emitted to a first position of the eye. In a second mode, the sensing light is emitted to a second position of the eye.

Abstract: This disclosure relates to protein complexes targeting CD47 and 4-1BB, and methods of use thereof. In one aspect, the protein complexes include one or more CD47-binding domains including all or a portion of the SIRP? extracellular regions, and one or more 4-1BB-binding domains including all or a portion of the 4-1BBL extracellular region.

Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.

Abstract: The invention relates to processes for preparing carbaprostacyclin analogues and intermediates prepared from the processes. The invention also relates to cyclopentenone intermediates in racemic or optically active form.

Abstract: A monitoring method and a monitoring system for a machine tool to machine a workpiece are provided. The monitoring method includes the following steps. First, a vibration signal of a spindle of the machine tool is detected. Next, a vibration feature value of the vibration signal is obtained. Whether the vibration feature value exceeds a threshold condition is determined, wherein the threshold condition is determined by a training model based on a predetermined surface quality of the workpiece. When the vibration feature value exceeds the threshold condition, a machining parameter of the machine tool is adjusted.

Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure located on the substrate, a second type semiconductor structure located on the first type semiconductor structure, an active structure located between the first type semiconductor structure and the second type semiconductor structure, a plurality of contact portions disposed between the first type semiconductor structure and the substrate, and a first conductive oxide layer, a second conductive oxide layer, a first insulating layer and a second insulating layer. The plurality of contact portions is separated from each other, and one of them includes a semiconductor and has a side wall. The first conductive oxide layer contacts the contact portion, and the second conductive oxide layer contacts the first conductive oxide layer. The first insulating layer contacts the side wall. The second insulating layer is disposed between the first insulating layer and the second conductive oxide layer.