Patents by Inventor Chun-Yu Lin

Chun-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240103375
    Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chih HO, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20240105720
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Publication number: 20240107776
    Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.
    Type: Application
    Filed: January 5, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Chieh LU, Chih-Yu CHANG, Yu-Chuan SHIH, Huai-Ying HUANG, Yu-Ming LIN
  • Publication number: 20240105849
    Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.
    Type: Application
    Filed: February 10, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Da-Zhi ZHANG, Chun-An LU, Chung-Yu CHIANG, Po-Nien CHEN, Hsiao-Han LIU, Jhon-Jhy LIAW, Chih-Yung LIN
  • Publication number: 20240083828
    Abstract: The present application relates to a system and a method for producing vinyl chloride. The system comprise a preheat unit, a gas-liquid separating unit, a heat-recovery unit, a heating unit and a thermal pyrolysis unit, and therefore heat energy of the thermal pyrolysis product can be efficiently recovered. Energy cost of the system can be efficiently lowered with the heat-recovery unit and the heating unit, and further prolonging operating cycle of the system.
    Type: Application
    Filed: June 28, 2023
    Publication date: March 14, 2024
    Inventors: Wen-Hsi HUANG, Sheng-Yen KO, Shih-Hong CHEN, Chun-Yu LIN
  • Patent number: 11923396
    Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wei Hsu, Tsai-Hao Hung, Chung-Yu Lin, Ying-Hsun Chen
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Publication number: 20240072158
    Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Sung-Hsin Yang, Jung-Chi Jeng, Ru-Shang Hsiao, Kuo-Min Lin, Z.X. Fan, Chun-Jung Huang, Wen-Yu Kuo
  • Publication number: 20240072136
    Abstract: A semiconductor structure includes a first transistor, a second transistor, a metal rail, and a first source/drain contact and a second source/drain contact. The first transistor has a gate structure, a first source/drain feature, and a second source/drain feature. The first source/drain feature and the second source/drain feature are on opposite sides of the gate structure. The second transistor has the gate structure, a third source/drain feature directly over the first source/drain feature, and a fourth source/drain feature directly over the second source/drain feature. The metal rail extends in an X-direction and adjacent to the gate structure in a Y-direction. The first source/drain contact and the second source/drain contact each has an L-shape in a Y-Z cross-sectional view. The first source/drain contact electrically connects the first source/drain feature to the metal rail. The second source/drain contact electrically connects the fourth source/drain feature to the metal rail.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Yu LIN, Chun-Fu CHENG, Hsiang-Hung HUANG
  • Patent number: 11914277
    Abstract: An illumination system for providing an illumination beam includes red, blue, and green light source modules, a first light combining element, and a light uniforming element. The red light source module includes a first red light emitting element emitting first red light and a second red light emitting element emitting second red light. A peak wavelength of the second red light is greater than a peak wavelength of the first red light. The blue light source module includes a first blue light emitting element emitting first blue light and a second blue light emitting element emitting second blue light. A peak wavelength of the second blue light is less than a peak wavelength of the first blue light. The green light source module generates green light. The first light combining element guides these lights into the light uniforming element, so that the illumination system outputs the illumination beam.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Hung-Yu Lin, Chi-Fu Liu, Chun-Hsin Lu, Chun-Li Chen
  • Patent number: 11917340
    Abstract: A projection device, including an illumination system, a control element, a driving element, a light valve, and a projection lens, is provided. The illumination system includes multiple light sources for providing multiple light beams to be combined into an illumination light beam. The driving element respectively drives the light sources in a first mode or a second mode, so that the light beams have respective luminous brightness, and the driving element is switched from the first mode to the second mode according to a first signal. The control element provides the first signal to the driving element according to an optical state or a time state of the projection device. The light valve is adapted to convert the illumination light beam into an image light beam. The projection lens is adapted to project the image light beam out of the projection device.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Chi-Fu Liu, Tsung-Hsin Liao, Chun-Li Chen, Hung-Yu Lin
  • Patent number: 11916084
    Abstract: A transparent display panel with driving electrode regions, circuit wiring regions, and optically transparent regions is provided. The driving electrode regions are arranged into an array in a first direction and a second direction. An average light transmittance of the circuit wiring regions is less than ten percent, and an average light transmittance of the optically transparent regions is greater than that of the driving electrode regions and the circuit wiring regions. The first direction intersects the second direction. The circuit wiring regions connect the driving electrode regions at intervals, such that each optically transparent region spans among part of the driving electrode regions. The transparent display panel includes first signal lines and second signal lines extending along the circuit wiring regions, and each circuit wiring region is provided with at least one of the first signal lines and at least one of the second signal lines.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: February 27, 2024
    Assignee: AUO Corporation
    Inventors: Chun-Yu Lin, Kun-Cheng Tien, Jia-Long Wu, Ming-Lung Chen, Shu-Hao Huang
  • Patent number: 11901480
    Abstract: The present disclosure provides a light-emitting device comprising a substrate with a topmost surface; a first semiconductor stack arranged on the substrate, and comprising a first top surface separated from the topmost surface by a first distance; a first bonding layer arranged between the substrate and the first semiconductor stack; a second semiconductor stack arranged on the substrate, and comprising a second top surface separated from the topmost surface by a second distance which is different form the first distance; a second bonding layer arranged between the substrate and the second semiconductor stack; a third semiconductor stack arranged on the substrate, and comprising third top surface separated from the topmost surface by a third distance; and a third bonding layer arranged between the substrate and the third semiconductor stack; wherein the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack are configured to emit different color lights.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: February 13, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Fu Huang, Chih-Chiang Lu, Chun-Yu Lin, Hsin-Chih Chiu
  • Patent number: 11901353
    Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Min Wu, Ming-Dou Ker, Chun-Yu Lin, Li-Wei Chu
  • Publication number: 20240047604
    Abstract: A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventors: Hsin-Chih Chiu, Chih-Chiang Lu, Chun-Yu Lin, Ching-Huai Ni, Yi-Ming Chen, Tzu-Chieh Hsu, Ching-Pei Lin
  • Patent number: 11884640
    Abstract: The invention relates to processes for preparing benzoprostacyclin analogues and intermediates prepared from the process, and the benzoprostacyclin analogues prepared therefrom. The invention also relates to cyclopentenone intermediates in racemic or optically active form.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: January 30, 2024
    Assignee: CHIROGATE INTERNATIONAL INC.
    Inventors: Chun-Yu Lin, Tzyh-Mann Wei, Shih-Yi Wei
  • Patent number: 11884613
    Abstract: The invention relates to processes for preparing carbaprostacyclin analogues and intermediates prepared from the processes. The invention also relates to cyclopentenone intermediates in racemic or optically active form.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: January 30, 2024
    Assignee: CHIROGATE INTERNATIONAL INC.
    Inventors: Chun-Yu Lin, Tzyh-Mann Wei, Shih-Yi Wei
  • Publication number: 20240025832
    Abstract: The invention relates to processes for preparing carbaprostacyclin analogues and intermediates prepared from the processes. The invention also relates to cyclopentenone intermediates in racemic or optically active form.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 25, 2024
    Applicant: CHIROGATE INTERNATIONAL INC.
    Inventors: CHUN-YU LIN, TZYH-MANN WEI, SHIH-YI WEI
  • Publication number: 20230416216
    Abstract: A racemic or optically enriched compound of Formula 1: wherein P is H or a protective group for hydroxyl groups; and X is Cl, Br, I, or —CH2CH2CH2COOR1, wherein R1 is C1-7-alkyl or C7-11-aralkyl.
    Type: Application
    Filed: September 14, 2023
    Publication date: December 28, 2023
    Applicant: CHIROGATE INTERNATIONAL INC.
    Inventors: CHUN-YU LIN, TZYH-MANN WEI, SHIH-YI WEI
  • Publication number: 20230421280
    Abstract: A time synchronization method for a time synchronization device, wherein the device is connected to a plurality of time synchronization domains through a plurality of ports, and the plurality of time synchronization domains use a plurality of PTP profiles. The method comprises determining whether each of the plurality of ports is a time receiving port or a time transmitting port; obtaining information of a grandmaster clock of the plurality of time synchronization domains; performing information conversion on the information of the grandmaster clock according to a PTP profile corresponding to each time transmitting port of the plurality of ports in the plurality of PTP profiles, so as to generate a plurality of clock information corresponding to each time transmitting port; and transmitting a corresponding clock information of the plurality of clock information to a corresponding time synchronization domain from each time transmitting port, so as to perform time synchronization.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 28, 2023
    Applicant: Moxa Inc.
    Inventors: Chi-Chuan Liu, Chun-Yu Lin, Chien-Yu Lai, Po-Hung Lin