Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: An image sensor includes a group of sensor units and a color filter layer disposed within the group of sensor units. The image sensor further includes a dielectric structure and a plurality of polarization splitters disposed corresponding to the color filter layer. Each of the plurality of polarization splitters has a first meta element extending in a first direction from top view and a second meta element extending in a second direction from top view. The second direction is perpendicular to the first direction.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

Abstract: A heat dissipation module includes a housing defining a receiving space for accommodating a fan, a turntable, and an expansion mechanism. The housing includes a top plate and two side walls connected to opposite ends of the top plate. The fan is configured for generating airflow from one side wall to the other. The turntable is connected to the expansion mechanism. The turntable rotates into a locked position to extend the expansion mechanism to protrude from the housing, and the turntable deviates from the locked position to retract the expansion mechanism back into the housing. An electronic device including the heat dissipation module is also provided.

Abstract: The optical device includes a first photodiode, a second photodiode, and a hybrid absorber. The hybrid absorber is disposed above the first photodiode and the second photodiode. The hybrid absorber includes a color filter layer and a plurality of metal-insulator-metal structures. The color filter layer includes a first color filter disposed on the first photodiode and a second color filter disposed on the second photodiode, in which the first color filter is different from the second color filter. The plurality of metal-insulator-metal structures are disposed above the first photodiode and free of disposed above the second photodiode.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures and a first epitaxial structure and a second epitaxial structure sandwiching one or more of the stack of semiconductor nanostructures. The semiconductor device structure also includes a backside conductive contact electrically connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the stack of semiconductor nanostructures. The semiconductor device structure further includes an insulating spacer beside a second portion of the backside conductive contact extending towards the second epitaxial structure.

Abstract: A knob on a touch panel includes a rotary wheel, a common pad, at least one sensing pad, a plurality of connectors and a conductive ring. The rotary wheel is mounted on the touch panel. The common pad is deployed on the touch panel. The at least one sensing pad is deployed on the touch panel. Each of the plurality of connectors is coupled between the rotary wheel and one pad among the at least one sensing pad and the common pad, to control each of the at least one sensing pad to be coupled to the common pad or not through the rotary wheel according to an operation of the knob. The conductive ring is deployed on a surface of the rotary wheel, to detect a touch object.

Abstract: A solid-state storage device is provided, which includes a controller and a non-volatile memory. The controller selects a first word line group from a plurality of word line groups obtained by classifying the word lines based on a read threshold voltage of each word line, and a representative word line corresponding to each word line group is set based on the read threshold voltage associated with each word line group. The controller uses the read threshold voltage of a first representative word line corresponding to the first word line group to read page data of the first representative word line. When the controller cannot correctly read the page data of the first representative word line using the read threshold voltage of the first representative word line, the controller updates the read threshold voltage of the first representative word line in the first word line group.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second dummy epitaxial layers disposed in first and second base structures, first and second active epitaxial layers disposed on the first and second dummy epitaxial layers, a first active nanostructured layer disposed adjacent to and in contact with the first active epitaxial layer, a second active nanostructured layer disposed adjacent to and in contact with the second active epitaxial layer, a dummy nanostructured layer disposed adjacent to and in contact with the second dummy epitaxial layer, a first gate structure surrounding the first active nanostructured layer, and a second gate structure surrounding the second active nanostructured layer and the dummy nanostructured layer.

Abstract: A physical layer module and a network module are provided. The network module includes the physical layer module and a media access control module. The physical layer module includes a group decoder, an input selection module, and a device module. The group decoder decodes a common input data signal generated according to a management data input/output signal to generate a group selection signal. The input selection module includes X input circuits being classified into M groups. The X input circuits generate X device input data according to the common input data signal and the group selection signal. The device module includes K physical layer devices classified into M groups. The K physical devices receive X device input data from the X input circuits. An m-th group corresponds to at least one input circuit and N[m] physical layer devices.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements and a color filter layer disposed above the photoelectric conversion elements. The color filter layer has a first color filter segment and a second color filter segment adjacent to the first color filter segment. The first color filter segment and the second color filter segment correspond to different colors. The solid-state image sensor also includes a shielding grid structure disposed between the first color filter segment and the second color filter segment. The shielding grid structure is divided into a first shielding segment and a second shielding segment. The solid-state image sensor further includes a meta structure disposed above the color filter layer. In a top view, the second shielding segment is formed as a triangle, a rectangle, or a combination thereof.

Abstract: A level shifter includes a cross-coupled transistor pair, first through third biased transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first biased transistor pair is controlled by a first reference voltage. The second biased transistor pair is controlled by a pair of differential control voltages. The third biased transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second biased transistor pair.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: A frequency offset (FO) estimation method includes: sampling a frequency-modulated repetition-coded segment of a packet to generate a plurality of samples; obtaining a frequency deviation (FD) value for each of a plurality of target samples selected from the plurality of samples; and estimating an FO value through accumulating complete FD values of the plurality of target samples.

Abstract: A lamp assembly includes a lamp, a medium and an assembling piece. The medium is configured to connect the lamp to a carrier. The assembling piece is disposed between the lamp and the medium, and is configured to connect the lamp to the medium, wherein the assembling piece includes a first part and a second part. The first part is configured to non-threadedly connect the lamp with the medium. The second part is configured to release the lamp from the medium.